1. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 1 Tomasulo Organization FP adders Add1 Add2 Add3 FP multipliers Mult1 Mult2 From Mem FP Registers Reservation Stations Common Data Bus (CDB) To Mem FP Ops Queue Load Buffers Store Buffers Load1 Load2 Load3 Load4 Load5 Load6

2. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 2 Three Stages of Tomasulo Algorithm 1.Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2.Execute—operate on operands (EX) When both operands ready, start to execute; if not ready, watch Common Data Bus for result 3.Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Normal data bus: data + destination (“go to” bus) Common data bus: data + source (“come from” bus) –64 bits of data + 4 bits of Functional Unit source address –Write if matches expected Functional Unit (produces result) –Does the broadcast Completion latencies for instructions in following example slides: clocks after start EX, +1 for LD; 2 for Fl.pt. +,-; 10 for *; 40 for /.

3. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 3 Reservation Station Components Op:Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of source operands for Op –Each store buffer has a V field, for the result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) –Note: Qj,Qk=0 => ready –Store buffers have only one Qi for RS producing result Busy: Indicates reservation station or FU is busy Time: After FU starts EX, number of cycles yet to do Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register.

4. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 4 Tomasulo Example Clock cycle counter FU count down Cycle instruction EXecution starts Instruction stream 3 Load/Buffers 3 FP Adder R.S. 2 FP Mult R.S. EX

5. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 5 Tomasulo Example Cycle 1 EX

6. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 6 Tomasulo Example Cycle 2 Note: Can have multiple loads outstanding EX 2

7. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 7 Tomasulo Example Cycle 3 Note: register names are removed (“renamed”) in Reservation Stations; MULTD issued; (clocks: +1 for LD; 2 FP +,-; 10 for *; 40 for /) Load1 completing; what is waiting for Load1? EX 2 3

8. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 8 Tomasulo Example Cycle 4 Load2 completing; what is waiting for Load2? Mult1, Add1 EX 2 3

9. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 9 Tomasulo Example Cycle 5 Timer starts down for Add1, Mult1 EX 2 3 5

10. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 10 Tomasulo Example Cycle 6 Issue ADDD despite name output-dependency on F6? EX 2 3 5

11. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 11 Tomasulo Example Cycle 7 Add1 (SUBD) completing; what is waiting for it? EX 2 3 5

12. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 12 Tomasulo Example Cycle 8 EX 2 3 5 8

13. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 13 Tomasulo Example Cycle 9 EX 2 3 5 8

14. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 14 Tomasulo Example Cycle 10 Add2 (ADDD) completing; what is waiting for it? F6 EX 2 3 5 8

15. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 15 Tomasulo Example Cycle 11 Write result of ADDD here? All quick instructions complete in this cycle! EX 2 3 5 8

16. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 16 Tomasulo Example Cycle 12 EX 2 3 5 8

17. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 17 Tomasulo Example Cycle 13 EX 2 3 5 8

18. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 18 Tomasulo Example Cycle 14 EX 2 3 5 8

19. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 19 Tomasulo Example Cycle 15 Mult1 (MULTD) completing; what is waiting for it? Mult2, F0 EX 2 3 5 8

20. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 20 Tomasulo Example Cycle 16 Must wait for Mult2 (DIVD) to complete (skip 38 no-new-action cycles … ) EX 2 3 5 16 8

21. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 21 … Tomasulo Example Cycle 55 EX 2 3 5 16 8

22. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 22 Tomasulo Example Cycle 56 Mult2 (DIVD) is completing; what is waiting for it? F10 EX 2 3 5 16 8

23. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 23 Tomasulo Example Cycle 57 Once again: In-order issue, out-of-order start of execution, and out-of-order completion. EX 2 3 5 16 8

24. 2/24; 3/1,3/11 (quiz was 2/22, QuizAns 3/8) CSE502-S11, Lec 08+9+10-ILP 24 Tomasulo Drawbacks Complexity –delays of 360/91, MIPS 10000, Alpha 21264, IBM PPC 620 (in CA:AQA 2/e, before it was in silicon!) Many associative stores (CDB) at high speed Performance limited by Common Data Bus –Each CDB must go to multiple functional units  high capacitance, high wiring density –Number of functional units that can complete per cycle limited to one! »Multiple CDBs  more FU logic for parallel assoc stores