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2. Building A CPU  We’ve built a small ALU l Add, Subtract, SLT, And, Or l Could figure out Multiply and Divide... 5.1  What about the rest l How do we deal with memory and registers? l What about control operations (branches)? l How do we interpret instructions?  The whole thing... l A CPU’s datapath deals with moving data around l A CPU’s control manages the data

3. Datapath Overview 5.1 Instruction Memory Registers Data Memory Read reg. num A Read reg. num B Write reg num Write reg data Read reg data A Read reg dataB Read address Instruction [31-0] Read address Write address Write data Read data Result PC Instructions: R-type: 3 registers I-type: 2 registers, Data Instructions: R-type: 3 registers I-type: 2 registers, Data ALU Computes on: R-type: 2 registers I-type: Register and data ALU Computes on: R-type: 2 registers I-type: Register and data Data to write into dest. register from: ALU or Memory Data to write into dest. register from: ALU or Memory Memory: Address from ALU Data to/from regs Memory: Address from ALU Data to/from regs Current Instruction: PC

4. Instruction Datapath 5.2 Instruction Memory Read address Instruction PC Add 4  Instructions will be held in the instruction memory  The instruction to fetch is at the location specified by the PC l Instr. = M[PC] Note: Regular instruction width (32 for MIPS) makes this easy Note: Regular instruction width (32 for MIPS) makes this easy After we fetch one instruction, the PC must be incremented to the next instruction All instructions are 4 bytes PC = PC + 4

5. R-type Instruction Datapath 5.2 Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Result Zero ALU Instruction  R-type Instructions have three registers l Two read (Rs, Rt) to provide data to the ALU l One write (Rd) to receive data from the ALU We’ll need to specify the operation to the ALU (later...) We might be interested if the result of the ALU is zero (later...) Read reg num A

6. Memory Operations 5.2 Data Memory Read address Write address Write data Read data Result Zero sign extend 16 32  Memory operations first need to compute the effective address l LW $t1, 450($s3) # E.A. = 450 + $s3 l Add together one register and 16 bits of immediate data l Immediate data needs to be converted from 16-bit to 32-bit  Memory then performs load or store using destination register Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Instruction

7. Branches 5.2 Add Result Sh. Left 2 Result Zero sign extend 16 32 PC + 4 To control logic Instruction  Branches conditionally change the next instruction l BEQ $2, $1, 42 l The offset is specified as the number of words to be added to the next instruction (PC+4) Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A  Control logic has to decide if the branch is taken l Uses ‘zero’ output of ALU  Take offset, multiply by 4 l Shift left two  Add this to PC+4 (from PC logic) offset

8. Integrating the R-types and Memory 5.3  R-types and Load/Stores are similar in many respects  Differences: l 2nd ALU source: R-types use register, I-types use Immediate l Write Data: R-types use ALU result, I-types use memory  Mux the conflicting datapaths together l Punt on the control logic for now Data Memory Read address Write address Write data Read data Result Zero sign extend 16 32 Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Instruction 0 1 1 0 Memory Datapath

9. Adding the instruction memory 5.3 Instruction Memory Add 4 Read address Instruction [31-0] Result PC Simply add the instruction memory and PC to the beginning of the datapath. Separate Instruction and Data memories are needed in order to allow the entire datapath to complete its job in a single clock cycle. Data Memory Read address Write address Write data Read data Result Zero 1 0 0 1 sign extend 16 32 Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A

10. Adding the Branch Datapath 5.3 Instruction Memory Add 4 Read address Instruction [31-0] Result PC Data Memory Read address Write address Write data Read data Result Zero 1 0 0 1 sign extend 16 32 Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Add Result Sh. Left 2 0 1 Now we have the datapath for R-type, I-type, and branch instructions. On to the control logic!

11. When does everything happen? 5.3 Instruction Memory Data Memory Add 4 Read address Instruction [31-0] Read address Write address Write data Read data Result Zero Result Sh. Left 2 0 1 1 0 0 1 sign extend PC 16 32 Read reg. num A Registers Read reg num B Write reg num Write reg data Read reg data A Read reg data B Read reg num A Combinational Logic: Just does it! Outputs are always just a function of its inputs (with some delay) Registers: Written at the end of the clock cycle. (Rising edge triggered). clk Single-Cycle Design