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331 W08.1Spring 2006 14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 8: Datapath Design [Adapted from Dave Patterson’s UCB CS152.

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Presentation on theme: "331 W08.1Spring 2006 14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 8: Datapath Design [Adapted from Dave Patterson’s UCB CS152."— Presentation transcript:

1 331 W08.1Spring :332:331 Computer Architecture and Assembly Language Spring 2006 Week 8: Datapath Design [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

2 331 W08.2Spring 2006 Review: Design Principles  Simplicity favors regularity l fixed size instructions – 32-bits l only three instruction formats  Good design demands good compromises l three instruction formats  Smaller is faster l limited instruction set l limited number of registers in register file l limited number of addressing modes  Make the common case fast l arithmetic operands from the register file (load-store machine) l allow instructions to contain immediate operands

3 331 W08.3Spring 2006  We're ready to look at an implementation of the MIPS  Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j  Generic implementation: l use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) l decode the instruction (and read registers) l execute the instruction  All instructions (except j ) use the ALU after reading the registers Why? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 DecodeExec

4 331 W08.4Spring 2006 Abstract Implementation View  Two types of functional units: l elements that operate on data values (combinational) l elements that contain state (sequential)  Single cycle operation  Split memory (Harvard) model - one memory for instructions and one for data AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

5 331 W08.5Spring 2006 Clocking Methodologies  Clocking methodology defines when signals can be read and when they can be written falling (negative) edge rising (positive) edge cycle time clock rate = 1/(cycle time) e.g., 10 nsec cycle time = 100 MHz clock rate 1 nsec cycle time = 1 GHz clock rate  State element design choices l level sensitive latch l master-slave and edge-triggered flipflops

6 331 W08.6Spring 2006 Review: State Elements  Set-reset latch  Level sensitive D latch l latch is transparent when clock is high (copies input to output) R S Q !Q RSQ(t+1)!Q(t+1) Q(t)!Q(t) 1100 clock D Q !Q clock D Q

7 331 W08.7Spring 2006 Review: State Elements, con’t  Race problem with latch based design …  Consider the case when D-latch0 holds a 0 and D- latch1 holds a 1 and you want to transfer the contents of D-latch0 to D-latch1 and vica versa l must have the clock high long enough for the transfer to take place l must not leave the clock high so long that the transferred data is copied back into the original latch  Two-sided clock constraint D clock Q !Q D-latch0 D clock Q !Q D-latch1 clock

8 331 W08.8Spring 2006 Review: State Elements, con’t  Solution is to use flipflops that change state (Q) only on clock edge (master-slave) -master (first D-latch) copies the input when the clock is high (the slave (second D-latch) is locked in its memory state and the output does not change) -slave copies the master when the clock goes low (the master is now locked in its memory state so changes at the input are not loaded into the master D-latch)  One-sided clock constraint l must have the clock cycle time long enough to accommodate the worst case delay path D clock Q !Q D-latch D clock Q !Q D-latch Q !Q D clock D Q

9 331 W08.9Spring 2006 Our Implementation  An edge-triggered methodology  Typical execution l read contents of some state elements l send values through some combinational logic l write results to one or more state elements  Assumes state elements are written on every clock cycle; if not, need explicit write control signal l write occurs only when both the write control is asserted and the clock edge occurs State element 1 State element 2 Combinational logic clock one clock cycle

10 331 W08.10Spring 2006 Fetching Instructions  Fetching instructions involves l reading the instruction from the Instruction Memory l updating the PC to hold the address of the next instruction l PC is updated every cycle, so it does not need an explicit write control signal l Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal Read Address Instruction Memory Add PC 4

11 331 W08.11Spring 2006 Decoding Instructions  Decoding instructions involves l sending the fetched instruction’s opcode and function field bits to the control unit Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit l reading two values from the Register File -Register File addresses are contained in the instruction

12 331 W08.12Spring 2006 Executing R Format Operations  R format operations ( add, sub, slt, and, or ) l perform the indicated (by op and funct) operation on values in rs and rt l store the result back into the Register File (into location rd) Note that Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite R-type: oprsrtrdfunctshamt 10

13 331 W08.13Spring 2006 Executing Load and Store Operations  Load and store operations l compute a memory address by adding the base register (in rs) to the 16-bit signed offset field in the instruction -base register was read from the Register File during decode -offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value l store value, read from the Register File during decode, must be written to the Data Memory l load value, read from the Data Memory, must be stored in the Register File I-Type: oprsrt address offset

14 331 W08.14Spring 2006 Executing Load and Store Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead

15 331 W08.15Spring 2006 Executing Branch Operations  Branch operations have to compare the operands read from the Register File during decode (rs and rt values) for equality ( zero ALU output) l compute the branch target address by adding the updated PC to the sign extended16-bit signed offset field in the instruction -“base register” is the updated PC -offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value and then shifted left 2 bits to turn it into a word address I-Type: oprsrt address offset

16 331 W08.16Spring 2006 Executing Branch Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

17 331 W08.17Spring 2006 Executing Jump Operations  Jump operations have to l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address J-Type: op jump target address

18 331 W08.18Spring 2006  We wait for everything to settle down l ALU might not produce “right answer” right away l we use write signals along with the clock edge to determine when to write (to the Register File and the Data Memory)  Cycle time determined by length of the longest path Our Simple Control Structure We are ignoring some details like register setup and hold times


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