1. Basic Structure Discharge Mechanism Wall Charge Concept Drive of PDP

2. Bus electrode Dielectric ITO electrodeMgO layer Barrier Phosphors Address Electrode Front panel Back panel Cell Structure of PDP

3. Electrode arrangement of SD PDP

4. Electrode covered with dielectricElectrode covered with dielectric dielectric limits currentdielectric limits current emission from both sideemission from both side AC-PDP V I V I Vf Y – X Making of Voltage (Over Vf) Y – X Making of Voltage (Over Vf) Wall Charge (Stop Discharge) Wall Charge (Stop Discharge) XY Discharge (Discharge Current) Discharge (Discharge Current) XY XY Discharge in AC PDP

5. Seed electron E-Field Discharge Mechanism - α Process Seed Electron : After seed electron generated in discharge space,it is accelerated by Electric field Seed Electron : After seed electron generated in discharge space,it is accelerated by Electric field Electron and Ion are generated by collision Between accelerated Electron and neutrality particle. Electron and Ion are generated by collision Between accelerated Electron and neutrality particle. Many Electrons and Ions are generated continuously by collision. It is end of first Discharge. Many Electrons and Ions are generated continuously by collision. It is end of first Discharge.

6. Discharge Mechanism - β Process secondary electron E-Field When Ion conflict with Cathode, it is generate 2 nd Electron. (A coefficient of 2 nd electron emission) When Ion conflict with Cathode, it is generate 2 nd Electron. (A coefficient of 2 nd electron emission) Electron and ion are generated from 2 nd electron’s acceleration and confliction. Electron and ion are generated from 2 nd electron’s acceleration and confliction. Many Electrons and Ions are generated continuously by collision. Many Electrons and Ions are generated continuously by collision.

7. Paschen Curve Repeat of α-process and β-process → Space insulation break down by increasing current → Discharge Self-sustained discharge Paschen Curve - Start voltage of Discharge (Vf : Minimum voltage for discharge) display a curve line of pressure * A function of an electrode distance. * Discharge Mechanism & Delay Repeat of α-process and β-process → Space insulation break down by increasing current → Discharge Self-sustained discharge Paschen Curve - Start voltage of Discharge (Vf : Minimum voltage for discharge) display a curve line of pressure * A function of an electrode distance. * Discharge Mechanism & Delay

8. Wall Charge XY XY XY Vex 0V Y X Vw1 Vw2 XY XY XY Vw1+Vex Vex - Vw2 Discharge Start Discharge Start No Discharge No Discharge Vex It is displayed differential discharge characteristics about same pulse by Wall Charge. : enable a picture V I Vf

9. Process of Sustain Discharge Vex 0V Y X XY Vw1+Vex Vex XY XY Vw1 Vex 0V X Y XY Vex-Vw2 Vw2 XY Vw2+Vex Vex XY Make wall charge Input electric field Discharge Sustain discharge Extinction of discharge (Wall charge Shield) Make wall charge Extinction of discharge (Wall charge Shield) Make wall charge Input electric field Discharge Sustain discharge

10. Sub-field Structure Frame Structure

11. 1 sub-field Image Process - ADS ResetAddressSustain Function Sustain Erase Wall Charge Set Issue Operation margin Contrast Short Time Function Sustain Erase Wall Charge Set Issue Operation margin Contrast Short Time Function Select On Cell Issue High Speed Low Voltage Low Failure Function Select On Cell Issue High Speed Low Voltage Low Failure Function Discharge On Cell Issue High Efficiency Low Voltage ERC Performance Function Discharge On Cell Issue High Efficiency Low Voltage ERC Performance

12. 1 sub-field Process - Reset

13. 1 sub-field Process - Address1

14. 1 sub-field Process - Address2

15. 1 sub-field Process - Address3

16. 1 sub-field Process - Address4

17. 1 sub-field Process - Address5

18. 1 sub-field Process - Address6

19. 1 sub-field Process - Address7

20. 1 sub-field Process - Address8

21. 1 sub-field Process - Address9

22. 1 sub-field Process - Sustain

23. Frame Structure - ADS SF1SF2SF3SF4SF5SF6SF7SF8 1..... 2 480 128T64T32T16T8T4T2T1T 1TV field (time) scan line address sustain sub-field Reset Period Address Period Sustain Period X Y1 Y2 Yn D

24. SF1SF2SF3SF4SF5SF6SF7SF8 Original Image 1..... 2 480 128T64T32T16T8T4T2T1T 1TV field (time) scan line address sustain sub-field 1 Picture Structure by 8 sub-field

25. Reset Period Address Period Sustain Period PDP Drive Pulse

26. Reset Period Sustain elimination discharge a. Very thin Pulse elimination method b. full width Pulse elimination method c. Self-erase elimination method d. Infirm discharge elimination method Wall Charge Set-up for Address : Actually, made wall charge profit of Ramp or RC pulse by infirm discharge Contrast : To make Back Ground bright interference Contrast Drive Margin

27. Based action : An address electrode and with a Y-electrode between generate discharge, Selected cell and not selected cell by Sustain Pulse have different characteristic with wall charge Write Address / Erase Address Non Address Failure : Address Pulse - Scan Pulse potential difference & Scan width a design High speed Addressing : It is important technique for high resolution, high brightness, low cost Discharge delay reduction by discharge condition improvement and drive waveform Low voltage Address : It is profitable of cost down by reduce resisting pressure Driver IC. Address Period

28. Pulse form : Input alternation pulse to X-electrode and Y-electrode Reality picture realizable sustain discharge : It is decide sustain discharge of wall charge difference separated with a cell between by address discharge Sustain drive Margin a. Drive of sustain discharge : decided by Panel’s Vs value b. The first stage drive : Reset discharge / Made Wall Charge selectivity by Address discharge and panel’s Vf Efficiency improve : It is many power consumption and need efficiency improve in Sustain discharge Sustain Period

29. PDP Drive Set Address Buffer Board Y Driver Board X Driver Board PowerSupplyBoard LogicBoard ImageProcessingBoard Scan Buffer Board Input : AC Power common in use Output : All voltages of each B’ds Image signal source X, Y Control signal Address Data signal RGB & Sync & Clock Y-output Scan power Scan signal Y-output Scan Pulse X-output Address output Port of Panel Electrode