Presentation is loading. Please wait.

Presentation is loading. Please wait.

Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic.

Similar presentations


Presentation on theme: "Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic."— Presentation transcript:

1 Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic

2 Teaser What does this do? Penn ESE370 Fall2014 -- DeHon 2

3 Previously Penn ESE370 Fall2014 -- DeHon 3

4 Impact of Capacitance Penn ESE370 Fall2014 -- DeHon 4

5 Today Pass Transistor Circuits C diff >0 Penn ESE370 Fall2014 -- DeHon 5

6 Pass Transistor Penn ESE370 Fall2014 -- DeHon 6

7 Identify Function What function? Penn ESE370 Fall2014 -- DeHon 7

8 Area Compare with CMOS circuit? Penn ESE370 Fall2014 -- DeHon 8

9 Output What is Vout if A=0, B=0? Penn ESE370 Fall2014 -- DeHon 9

10 Output What is Vout if A=1, B=0, notB=1? Penn ESE370 Fall2014 -- DeHon 10

11 Output Is this a restoring gate? Penn ESE370 Fall2014 -- DeHon 11

12 Output What does output look like (DC transfer)? –(B=1, notB=0, sweep A, notA=CMOS inv(A)) Penn ESE370 Fall2014 -- DeHon 12

13 Pass TR transfer (B=1) Penn ESE370 Fall2014 -- DeHon 13

14 CMOS Inverter Transfer Penn ESE370 Fall2014 -- DeHon 14

15 Reasonable Input to CMOS Inverter? Penn ESE370 Fall2014 -- DeHon 15

16 Pass tr xor2 with inv restore Penn ESE370 Fall2014 -- DeHon 16

17 Compare CMOS Is this a fair comparison? Penn ESE370 Fall2014 -- DeHon 17

18 Required to use? What need to add to make substitutable with CMOS? Penn ESE370 Fall2014 -- DeHon 18

19 Restore Output Penn ESE370 Fall2014 -- DeHon 19

20 Restore Output Area? (compare to CMOS) Penn ESE370 Fall2014 -- DeHon 20

21 Chain Together Penn ESE370 Fall2014 -- DeHon 21

22 Analyze Stage Penn ESE370 Fall2014 -- DeHon 22

23 Analyze Stage What’s different about this? Penn ESE370 Fall2014 -- DeHon 23

24 Delay B=0, C diff =0? Penn ESE370 Fall2014 -- DeHon 24

25 Equivalent RC Circuit Penn ESE370 Fall2014 -- DeHon 25

26 Circuit Penn ESE370 Fall2014 -- DeHon 26

27 Delay B=1, C diff =0? Penn ESE370 Fall2014 -- DeHon 27

28 Equivalent RC Circuit Penn ESE370 Fall2014 -- DeHon 28

29 Circuit Penn ESE370 Fall2014 -- DeHon 29

30 Circuit What’s different about this? Penn ESE370 Fall2014 -- DeHon 30

31 C diff >0 Penn ESE370 Fall2014 -- DeHon 31

32 Contact/Diffusion Capacitance C j – diffusion depletion C jsw – sidewall capacitance L S – length of diffusion Penn ESE370 Fall2014 -- DeHon 32 LSLS

33 Impact of Capacitance Penn ESE370 Fall2014 -- DeHon 33

34 Inverter Delay Delay driving another inverter? –Include Cdiff=  Cgate Penn ESE370 Fall2014 -- DeHon 34 W=1

35 Delay B=1, C diff =  C g ? Penn ESE370 Fall2014 -- DeHon 35

36 Equivalent RC Circuit? Penn ESE370 Fall2014 -- DeHon 36

37 Equivalent RC Circuit Penn ESE370 Fall2014 -- DeHon 37

38 Bonus (time permit) What does this do? Penn ESE370 Fall2014 -- DeHon 38 A B More examples in book.

39 Idea There are other circuit disciplines Can use pass transistors for logic –Sometimes gives area or delay win Penn ESE370 Fall2014 -- DeHon 39

40 Admin Project –Hopefully done with baseline –Ron office hours today –Get started on design-space exploration and optimization Penn ESE370 Fall2014 -- DeHon 40


Download ppt "Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic."

Similar presentations


Ads by Google