1. J. Linnemann, MSU 12/16/2015 1 L2 Status James T. Linnemann MSU Collaboration Meeting September 14, 2001

2. J. Linnemann, MSU 12/16/2015 2 Who? l Now commissioning: Arizona, Columbia, Maryland, Michigan/CDF MSU, Munich, Nebraska, NIU, Oklahoma Saclay, Stony Brook, UIC, Virginia Fermilab ESE (Green, Kwarciany, Zmuda) l Coming Soon BU, Florida State, Orsay A lot of good, hardworking people are responsible for L2 progress.

3. J. Linnemann, MSU 12/16/2015 3 Infrastructure l Power, cooling, cabling all in place except Intra-crate cables Last run of muon cables being re-cut l Safety clearance for power in process l All cards needed built and on site except last 11 alphas being assembled this week

4. J. Linnemann, MSU 12/16/2015 4 FIC: G-link receiver (all crates but muon) l FPGA code being tweaked Some vme problems remain ‚commissioning modes only; progress being made Extra data word in G-link? ‚Fix being tested FPGA compiler problems probably resolved ‚Distraction: “test” version used nonexistent resources Fermilab/ESE support for commissioning ‚Met this week with Saclay experts

5. J. Linnemann, MSU 12/16/2015 5 MBT workhorse I/O card l 31 cards in hand (24 work; 16 at Fermi) 4 need diagnosis/repair; 3 dead; 11+6 needed Before install: stable SCL firmware ‚Estimate: September/October installation l firmware all written; being debugged (good turnaround) ‚Scl_init sequence; L1, L2 busy (easier) Multi-card broadcast: need testing at FNAL 128 bit fanoutneeds testing at FNAL with Edmunds: Oct Some marginal timing being chased Results write to Global: needs to be re-integrated ‚May need to tweak output amplitude Monitoring functions: need to test at FNAL

6. J. Linnemann, MSU 12/16/2015 6 Alpha l First Production: 4-6 fully work (7 max); 2 back soon; break/fix about 1/week ‚Most: multiple vias fixed and a BGA replaced 17+2 abandoned ‚Broken CIA BGA not replaceable (center of board; vias too fragile) PIO to Alpha not working (firmware)early October ‚concentrate on 1 Alpha/crate l Second Production: Pre-production boards work ‚DMA fixes incorporated in layout ‚Learned can successfully replace CIA BGA (better than unreliable socket!) ‚new supplier for raw boards, better assembly (failures diagnosed; site visits) 11 more being built now: earliest end September l Need 15 for nominal system (+7 for test stand)

7. J. Linnemann, MSU 12/16/2015 7 Beta replacement processor l Intel Compact PCI card 2-3  Alpha in CPU ‚First card received and being tested l Hold in 9u card with custom devices (3 BGA’s) Universe Chip VME interface commercial 64-bit PCI interface chip Mbus and other logic in FPGA l Good start on low-level software Prep for PCI device drivers l Schedule: (quote soon) Schematic done; starting layout Firmware specs written; starting Verilog coding soon Prototypes available for testing December Production: early summer

8. J. Linnemann, MSU 12/16/2015 8 CIC and SFO l CIC (L2Mu input card) installed; inputs cabled l SFO (fanout): all but 2 at Fermi Needed by Muon system, and test stand Very useful for commissioning May have other uses during running All cards work in most important modes ‚For one mode, have to hand-select cards ‚ Only need 2 working in 1:12 fanout mode ‚ Investigating why only half do, but half of 25 is plenty

9. J. Linnemann, MSU 12/16/2015 9 SLIC l Basic Operating System done l First algorithm tests (Mu Central) OK Meet speed and efficiency requirements Other algorithms ready for download ‚tested in emulator l Implementing monitoring scheme

10. J. Linnemann, MSU 12/16/2015 10 Miscellaneous Interface Hardware l 16 to 128 bit mux add-on to MBT (UMd) Returns L2 trigger mask to L2HWFW Sep/Oct l L1HWFW to L2 Global (via FIC) (MSU) Optical Split: L1 trigger mask Aug/Oct ‚dummy content: fixed + event ID l Monitoring of Alphas by L1 Scalers (MSU) Passive cable formatting card Oct

11. J. Linnemann, MSU 12/16/2015 11 Commissioning At Last L1SCL-MBT-Alpha-VBD-L3 milestone met One channel “data”, real frame software, in MCH ‚Need to verify format from SAM Muon system has seen real inputs-CIC-SLIC ‚L1format needs correction ‚Scintformat OK but L2&timing interfere: errors ‚MDTformat OK ‚PDTunformatted: October? l Current tests: SCL_INIT for MBT-Alpha (for permanent MCH running) Add 2 nd channel of data (FIC-MBT-Alpha-VBD-L3) real algorithms into SLIC; timingFwd Mu already Muon: 2 nd or 3 rd input: CIC-SLIC-MBT-Alpha-VBD-L3 One event pushed through STT prototype vertical slice ‚FRC, STC, TFC: CTT roads, SMT clusters, fit

12. J. Linnemann, MSU 12/16/2015 12 Arrival of L2 Inputs When inputs steadily available (subset, full) l L1 Trigger Mask to Global (August, October) l Cal(September?, November?) l Muon Trigger (L2 software not tested)(June, November) Detector(August,October?) l CTT,CPS(October,November) l FPS(November,December) l COOR programming September?

13. J. Linnemann, MSU 12/16/2015 13 Online Software ( & Risks ) l Alpha: Much of structural software exists in simulation ‚Control/data flow for preprocessor and global Loader and modified Linux kernel; Developing drivers in EBSDK (fast turnaround); check in Linux Draft drivers/setup for MBT and event loop ‚Some alpha firmware problems (PIO needed for A-W split) ‚SCL_INIT—in progress (complex) ‚VME driver, buffer allocation (OK) ‚Verify byte order etc to L3 Error logging and beginnings of monitoring: testing Linking, downloading to Worker;Linux 7.1 releases needed Admin/Worker control; data flow software ‚few Alphas, so concentrate on 1-alpha crate for now l SLIC: Basic operating system in place monitoring; algorithms need download; scl_init

14. J. Linnemann, MSU 12/16/2015 14 Online Software Plans  Event data flow late Aug l Worker with filter code Sept Multi-alpha (as available)Oct/Nov ‚interrupts for speed as neededDec/Jan l Coor script downloading via TCC: Late Sept Till then, configure from hand-edited file ‚Online and in TSIM l Data Flow Monitoring testSept/Oct ‚Errorlogger to screen/S.E.S. Oct/Dec? l Global + PreprocessorOct-Nov FILTERING! (if have enough inputs…) l Verification: online vs. TSIM 1 st version running now; testing data capture Needs pretty good data to be usefulOct/Nov?

15. J. Linnemann, MSU 12/16/2015 15 Algorithms: in TSIM, downloadable; some L1SIM problems l MuL1; Central alpha, DSP working, ready to download output fmts need update Fwd DSP in CVS; next release (alpha already there) l CTTbase algorithm, tau working Tau tuning, slow movers waiting for postdoc hire when? l PS CPSrunning in TSIM; needs better L1 FPS written not released (no L1PS) when? l Cal all running in TSIM e = Run 1B L1.5 j merge needs work (interference with beta) MET= L1for now l Globalsome running in TSIM now e(cal,cps,track), j(cal); tracks; deta, dphi(e: fps-ready) Ht, Mass, MET; rsep coming Mu(with ctt), but no tau l Need Studies, Timing, Tuning! Lost 2 maintainers

16. J. Linnemann, MSU 12/16/2015 16 Summary l Commissioning is underway in earnest Some real inputs—need more to do physics ‚Mu, cal, ctt, cps is probable order Most hardware in hand ‚Remaining alphas soon, I hope Firmware written; commissioning it now ‚MBT, Alpha, FIC l Crucial scale-up tests in coming weeks ‚All hardware in crates ‚Multiple inputs ‚Algorithm downloads

17. J. Linnemann, MSU 12/16/2015 17 Board Summary: Dates, Risks l SLICJanuary 2001 Monitoring software l Crates/Power/CablesSeptember ORC; CIC crate l FICSeptember? Commission; FPGA code problems? l MBT September? FPGA code l Alphanow; September Fragility of 4-6 from 1 st production PIO firmware Fallback: Beta—next year l CIC,SFOAugust; September? Install/Commission l Crate population, intra-crate cablingSeptember/October

18. J. Linnemann, MSU 12/16/2015 18 Progress since Feb l Alpha cards for commissioning; start final production Fixed DMA; Beta started l FIC Fixed output signal; FPGA work resumed l MBT All firmware written/drivers (being debugged) Integration testing with Alpha at 2 sites multi-channel DMA, capture of SCL input info l CIC/SFO built l All power, most cabling l Software Drivers for all devices written (being tested) Most algorithms in TSIM l Real data sources in mu l data flow L1SCL to L3

19. J. Linnemann, MSU 12/16/2015 19 How Many Alphas? 15 + test stand in 2001 7

20. J. Linnemann, MSU 12/16/2015 20 Where do we put our Alphas? Staging; rotating tests; A+W Aug-Sept (5-10) l 1 Maryland l 2 Test Stand/UIC l 1-2 Global l 1-2 Mu/Cal (turns?) Oct-Nov (5 to20) l 2-4 Mu l 1-4 Cal l 1-2 Global l 2-5 CTT,PS l 1-2 Test stand l 1 Maryland/Va l 1-4 UIC/Test Stand

21. J. Linnemann, MSU 12/16/2015 21 L2 Cards & Names build/ operate l FICG-link to Hotlink Renardy, Mur (Saclay) Buehler, Kostas, Heinmiller (UIC) Kwarciany (FNAL) l MBTHotlink, MBus, other I/O Giganti, Bard, Baden (Maryland) +Toole/ Schwienhorst l Alphamain processor (Campbell, Miller UM); Buehler,Heinmiller,Kostas, Varelas (UIC) Hirosky (UVa) Kwarciany/Zmuda (FNAL) l SLIC  Processor Sippach, Evans (Nevis/Columbia) Kothari, Christos (CU); Maciel, Fortner,Uzunyan(NIU) Christiansen, Strohmer, Trefzger, Schaile (Munich) l CIC, SFO SMB to RJ45 Hotlink; Hotlink fanout Lewis, Snow (Nebraska)Tester: Johns (UAZ) Hansen, Baldin, (Anderson) FNAL Maciel, Kothari, Fortner l VBD; Bit3 L3, TCC Zeller, Cutts; Commercial Mattingly (Brown); Schwienhorst (MSU)

22. J. Linnemann, MSU 12/16/2015 22 Commissioning l Limiting factors: Stable, fully functional L2 Cards (ouch) ‚MBT’s with full functionality ‚FIC: lack of on-site expertise ‚ Lack of reliable system to modify firmware ‚Alpha: lack of firmware expertise on-site Manpower (trained—getting better) ‚Big conflict with ‚ Prototype testing (MBT, CIC, SFO) ‚ Production debugging (Alpha) ‚ Beta (fallback plan for Alpha) ‚Rick Kwarciany is part-time integration engineer Alpha software for commissioning ‚Limited, in turn, by above problems Availability of inputs ‚Real, or test; becoming limiting factor

23. J. Linnemann, MSU 12/16/2015 23 Preprocessor Chains: Commissioning Scale..20..40..20..40..60..80..100% l 0% l 0% Connectivity not tested l 20 l 20 Signal compatibility demonstrated l 40 l 40 Correct data transfer once or usually; or physical layer (BIST?) full speed, error rate OK l 60 Fake data, repeated transfers, error rate OK l 80 Full speed fake data, error rate ok, >1 day l 100% Real data full cards, in system, full speed, errors OK, > 1 week

24. J. Linnemann, MSU 12/16/2015 24 Preprocessor Chains 0%..20%..40 0%..20%..40..60..80..100% l L1DFE FIC..SFO MBT Alpha L3 (test stand) l L1Cal FIC SFO MBT Alpha VBD L3 (DAQ) l MuFE CIC SLIC SFO MBT Alpha L3 l Mutest CICSFO l Mutest CIC SFO SLIC SFO MBT Alpha L3 l Alpha MBTMBT l Alpha MBT MBT Alpha (2 crates) l Alpha Alpha l L1SCL MBT Alpha VBD L3 l MBT SFO patch panel MBTAlpha VBD l MBT SFO patch panel MBT Alpha VBD L3 (test stand) l L1SCL MBT l L1SCL MBT SFO SLIC MBT Alpha l L1FW FIC MBT Alpha l Alpha MBT l Alpha MBT L2FW….