1. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 1 Computer Systems Virtual Memory

2. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 2 A System with Virtual Memory Address Translation: Hardware converts virtual addresses to physical addresses via lookup table (page table) CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses

3. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 3 VM advance #1: Caching Tool Data 243 17 105 0: 1: N-1: X Object Name Location D: J: X: 1 0 On Disk “Cache”Page Table DRAM Cache (Main Memory) –Each allocated page of virtual memory has entry in page table –Mapping from virtual pages to physical pages From uncached form to cached form –Page table entry even if page not in memory Specifies disk address

4. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 4 Locating an Object in a “Cache” SRAM Cache (level 1 en level 2) –Tag stored with cache line –Maps from cache block to memory blocks From cached to uncached form Save a few bits by only storing tag –No tags for blocks not in cache –Hardware retrieves information can quickly match against multiple tags X Object Name TagData D243 X 17 J105 0: 1: N-1: = X? “Cache”

5. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 5 Memory Mountain

6. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 6 Page Faults (like “Cache Misses”) What if an object is on disk rather than in memory? –Page table entry indicates virtual address not in memory –OS exception handler invoked to move data from disk into memory current process suspends, others can resume OS has full control over placement, etc. Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses Before fault After fault CPU

7. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 7 Processor Hardware Addr Trans Mechanism fault handler Main Memory Secondary memory a a'  page fault physical address OS performs this transfer (only if miss) virtual addresspart of the on-chip memory mgmt unit (MMU) VM Address Translation: Hardware vs Software

8. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 8 virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–10p–1p Page offset bits don’t change as a result of translation VM Address Translation Parameters –P = 2 p = page size (bytes). –N = 2 n = Virtual address limit –M = 2 m = Physical address limit

9. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 9 virtual page number (VPN)page offset virtual address physical page number (PPN)page offset physical address 0p–1pm–1 n–10p–1p page table base register if valid=0 then page not in memory valid physical page number (PPN) access VPN acts as table index PTEA = PTE Address Translation via Page Table

10. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 10 CPU Trans- lation Cache Main Memory VAPA miss hit data Integrating VM and Cache Most Caches “Physically Addressed” –Allows multiple processes to have blocks in cache at same time –Cache doesn’t need to be concerned with protection issues (Access rights checked as part of address translation) Perform Address Translation Before Cache –But this involves a memory access itself (of the PTE) –Of course, page table entries can also become cached

11. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 11 CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss Speeding up Translation with a dedicated cache “Translation Lookaside Buffer” (TLB) –Small hardware cache in MMU –Maps virtual page to physical page numbers –Contains complete PTEs for small number of pages

12. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 12 What do you know? (ow133)cpuid This system has a Genuine Intel(R) Pentium(R) 4 processor Processor Family: F, Extended Family: 0, Model: 2, Stepping: 7 Pentium 4 core C1 (0.13 micron): core-speed 2 Ghz - 3.06 GHz (bus-speed 400/533 MHz) Instruction TLB: 4K, 2M or 4M pages, fully associative, 128 entries Data TLB: 4K or 4M pages, fully associative, 64 entries 1st-level data cache: 8K-bytes, 4-way set associative, sectored cache, 64-byte line size No 2nd-level cache or, if processor contains a valid 2nd-level cache, no3rd-level cache Trace cache: 12K-uops, 8-way set associative 2nd-level cache: 512K-bytes, 8-way set associative, sectored cache, 64-byte line size

13. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 13 VM advance #2: Memory Management Multiple processes in physical memory. How do we resolve address conflicts? –what if two processes access something at the same address? kernel virtual memory Memory mapped region forshared libraries runtime heap (via malloc) program text (.text) initialized data (.data) uninitialized data (.bss) stack forbidden 0 %esp memory invisible to user code the “brk” ptr Linux/x86 process memory image

14. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 14 Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 Address Translation 0 0 N-1 0 M-1 VP 1 VP 2 PP 7 PP 10 (e.g., read/only library code) Solution: Separate Virt. Addr. Spaces –Each process has its own virtual address space operating system controls how virtual pages as assigned to physical memory... Virtual Address Space for Process 2:

15. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 15 vm_next Linux Organizes VM as Collection of “Areas” task_struct mm_struct pgd mm mmap vm_area_struct vm_end vm_prot vm_start vm_end vm_prot vm_start vm_end vm_prot vm_next vm_start process virtual memory text data shared libraries 0 0x08048000 0x0804a020 0x40000000 –pgd: page directory address –vm_prot: read/write permissions for this area –vm_flags shared with other processes or private to this process vm_flags

16. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 16 VM advance #3: Protection Page table contains access rights information –hardware enforces this protection (trap into OS if violation occurs) Process i: Physical AddrRead?Write? PP 9YesNo PP 4Yes XXXXXXX No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical AddrRead?Write? PP 6Yes PP 9YesNo XXXXXXX No VP 0: VP 1: VP 2:

17. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 17 Linux Page Fault Handling vm_area_struct vm_end r/o vm_next vm_start vm_end r/w vm_next vm_start vm_end r/o vm_next vm_start process virtual memory text data shared libraries 0 Is the VA legal? –i.e. is it in an area defined by a vm_area_struct? –if not then signal segmentation violation (e.g. (1)) Is the operation legal? –i.e., can the process read/write this area? –if not then signal protection violation (e.g., (2)) If OK, handle fault (3) write read 1 2 3

18. University of Amsterdam Computer Systems – virtual memory Arnoud Visser 18 Assignment Practice Problem 10.1: Find the largest possible virtual address. !At some point in your lifetime, you find yourself complaining about the cramped 64-bit address space in your computer!