1. Virtual Memory Topics Motivations for VM Address translation Accelerating translation with TLBs CS 105 “Tour of the Black Holes of Computing!”

2. – 2 – CS 105 What Is Virtual Memory? If you think it’s there, and it’s there…it’s real. If you think it’s not there, and it’s there…it’s transparent. If you think it’s there, and it’s not there…it’s imaginary. If you think it’s not there, and it’s not there…it’s nonexistent. Virtual memory is imaginary memory: it gives you the illusion of a memory arrangement that’s not physically there.

3. – 3 – CS 105 Motivations for Virtual Memory Use physical DRAM as cache for the disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory (more common modern case) Simplify memory management Multiple processes resident in main memory Each with its own address space Only “active” code and data is actually in memory Allocate more memory to process as needed Provide protection One process can’t interfere with another Because they operate in different address spaces User process cannot access privileged information Different sections of address spaces have different permissions

4. – 4 – CS 105 Motivation #1: DRAM as “Cache” for Disk Full address space is quite large: 32-bit addresses: ~4,000,000,000 (4 billion) bytes 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes Disk storage is ~250X cheaper than DRAM storage 1 TB of DRAM: ~ $28,000 (667 MHz, late 2008 prices) 1 TB of disk: ~ $115 To get cost-effective access to large amounts of data, bulk of data must be stored on disk 4GB: ~$56 1 TB: ~$115 2 MB: ~$150 Disk DRAMSRAM

5. – 5 – CS 105 Levels in Memory Hierarchy CPU regs CacheCache Memory disk size: speed: $/Mbyte: line size: 32 B 0.3 ns 4 B RegisterCacheMemoryDisk Memory 32 KB-4MB 2 ns? $75/MB 32 B 4096 MB 7.5 ns $0.014/MB 4 KB 1 TB 8 ms $0.00012/MB larger, slower, cheaper 8 B32 B4 KB cachevirtual memory

6. – 6 – CS 105 DRAM vs. SRAM as a “Cache” DRAM vs. disk is more extreme than SRAM vs. DRAM Access latencies: DRAM ~10X slower than SRAM Disk ~100,000X slower than DRAM Importance of exploiting spatial locality: First byte is ~100,000X slower than successive bytes on disk »vs. ~4X improvement for page-mode vs. regular accesses to DRAM Bottom line: Design decisions made for disk caches in DRAM driven by enormous cost of misses DRAM SRAM Disk

7. – 7 – CS 105 Impact of Properties on Design If disk cache were organized like L1/L2 cache, how would we set following design parameters? Line size? Large, since disk better at transferring large blocks Associativity? High, to mimimize miss rate Write through or write back? Write back, since can’t afford small writes to disk What would the impact of these choices be on: Miss rate Extremely low: << 1% Hit time Must match cache/DRAM performance Miss latency Very high: ~10ms Tag storage overhead Low, relative to block size

8. – 8 – CS 105 Locating an Object in a “Cache” Review of SRAM (L1/L2) Cache Tag stored with cache line Maps from cache block to memory blocks From cached to uncached form Save a few bits by only storing tag of blocks that are in cache No tag for block not in cache Hardware retrieves information Can quickly match against multiple tags X Object Name TagData D243 X 17 J105 0: 1: N-1: = X? “Cache”

9. – 9 – CS 105 Locating an Object in a “Cache” Data 243 17 105 0: 1: N-1: X Object Name Location D: J: X: 1 0 On Disk “Cache”Page Table DRAM (disk) Cache Each allocated page of virtual memory has entry in page table Mapping from virtual to physical pages From uncached form to cached form Page table entry (tag) even if page not in memory Specifies disk address Only way to know where to find page OS retrieves information from disk as needed

10. – 10 – CS 105 A System with Physical Memory Only Examples: Most Cray machines, early PCs, nearly all embedded systems, etc. Addresses generated by the CPU correspond directly to bytes in physical memory CPU 0: 1: N-1: Memory Physical Addresses

11. – 11 – CS 105 A System with Virtual Memory Examples: Workstations, servers, modern PCs, etc. Address Translation: Hardware converts virtual addresses to physical ones via OS-managed lookup table (page table) CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses

12. – 12 – CS 105 Page Faults (Like “Cache Misses”) What if object is on disk rather than in memory? Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory - VM and Multiprogramming are symbiotic Current process suspends, others can resume OS has full control over placement, etc. CPU Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses Before fault After fault

13. – 13 – CS 105 Servicing Page Fault Processor signals controller Read block of length P starting at disk address X and store starting at memory address Y Read occurs Direct Memory Access (DMA) Under control of I/O controller I/O controller signals completion Interrupt processor OS resumes suspended process disk Disk disk Disk Memory-I/O bus Processor Cache Memory I/O controller I/O controller Reg (2) DMA Transfer (1) Initiate Block Read (3) Read Done

14. – 14 – CS 105 Motivation #2: Memory Mgmt Multiple processes can reside in physical memory. How do we resolve address conflicts? What if two processes access something at same address? kernel virtual memory Memory-mapped region for shared libraries runtime heap (via malloc) program text (.text) initialized data (.data) uninitialized data (.bss) stack forbidden 0 %esp memory invisible to user code the “brk” pointer Linux/x86 process memory image

15. – 15 – CS 105 Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 Address Translation 0 0 N-1 0 M-1 VP 1 VP 2 PP 7 PP 10 (e.g., read/only library code) Solution: Separate Virtual Address Spaces Virtual and physical address spaces divided into equal-sized blocks Blocks are called “pages” (both virtual and physical) Each process has its own virtual address space Operating system controls how virtual pages are assigned to physical memory... Virtual Address Space for Process 2:

16. – 16 – CS 105 Motivation #3: Protection Page table entry contains access-rights information Hardware enforces this protection (trap into OS if violation occurs) Page Tables Process i: Physical AddrRead?Write? PP 9YesNo PP 4Yes XXXXXXX No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical AddrRead?Write? PP 6Yes PP 9YesNo XXXXXXX No VP 0: VP 1: VP 2:

17. – 17 – CS 105 VM Address Translation Virtual Address Space V = {0, 1, …, N – 1} Physical Address Space P = {0, 1, …, M – 1} M < N (Usually—PDP-11, 32-bit Pentiums violate this) Address Translation MAP: V  P  {  } For virtual address a: MAP(a) = a′ if data at virtual address a is at physical address a′ in P MAP(a) =  if data at virtual address a is not in physical memory »Either invalid or stored on disk

18. – 18 – CS 105 VM Address Translation: Hit Processor Hardware Addr Trans Mechanism Main Memory a a' physical addressvirtual address part of on-chip memory mgmt unit (MMU)

19. – 19 – CS 105 VM Address Translation: Miss Processor Hardware Addr Trans Mechanism fault handler Main Memory Secondary memory a a'  page fault physical address OS performs this transfer (only if miss) virtual address part of on-chip memory mgmt unit (MMU)

20. – 20 – CS 105 virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–10p–1p Page offset bits don’t change as a result of translation VM Address Translation Parameters P = 2 p = page size (bytes). N = 2 n = Virtual-address limit M = 2 m = Physical-address limit

21. – 21 – CS 105 Page Tables Memory-resident page table (physical page or disk address) Physical Memory Disk Storage (swap file or regular file system file) Valid 1 1 1 1 1 1 1 0 0 0 Virtual Page Number

22. – 22 – CS 105 Address Translation via Page Table virtual page number (VPN)page offset virtual address physical page number (PPN)page offset physical address 0p–1pm–1 n–10p–1p page table base register if valid=0 then page not in memory valid physical page number (PPN)access VPN acts as table index

23. – 23 – CS 105 Page Table Operation Translation Separate (set of) page table(s) per process VPN forms index into page table (points to a page table entry)

24. – 24 – CS 105 Page Table Operation Computing physical address Page Table Entry (PTE) provides information about page If (valid bit = 1) then page is in memory. »Use physical page number (PPN) to construct address If (valid bit = 0) then page is on disk (or nonexistent) »Page fault

25. – 25 – CS 105 Page Table Operation Checking protection Access-rights field indicates allowable access E.g., read-only, read-write, execute-only Typically support multiple protection modes (e.g., kernel vs. user) Protection-violation fault if user doesn’t have necessary permission

26. – 26 – CS 105 Integrating VM and Cache Most caches “physically addressed” Accessed by physical addresses Allows multiple processes to have blocks in cache at same time else context switch == cache flush Allows multiple processes to share pages Cache doesn’t need to be concerned with protection issues Access rights checked as part of address translation Perform address translation before cache lookup Could involve memory access itself (to get PTE) So page table entries can also be cached CPU Trans- lation Cache Main Memory VAPA miss hit data

27. – 27 – CS 105 Speeding up Translation With a TLB “Translation Lookaside Buffer” (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss

28. – 28 – CS 105 Address Translation With a TLB virtual address virtual page number page offset physical address n–10p–1p validphysical page numbertag validtagdata = cache hit tagbyte offset index = TLB hit TLB Cache...

29. – 29 – CS 105 Simple Memory System Example Addressing 14-bit virtual addresses 12-bit physical addresses Page size = 64 bytes 131211109876543210 11109876543210 VPO PPOPPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset)

30. – 30 – CS 105 Simple Memory System Page Table Only first 16 entries shown VPNPPNValidVPNPPNValid 0028108131 01–009171 023310A091 030210B–0 04–00C–0 051610D2D1 06–00E111 07–00F0D1

31. – 31 – CS 105 Simple Memory System TLB TLB 16 entries 4-way associative 131211109876543210 VPO VPN TLBI TLBT SetTagPPNValidTagPPNValidTagPPNValidTagPPNValid 003–0090D100–007021 1032D102–004–00A–0 202–008–006–003–0 307–0030D10A34102–0

32. – 32 – CS 105 Simple Memory System Cache Cache 16 lines 4-byte line size Direct mapped 11109876543210 PPOPPN CO CI CT IdxTagValidB0B1B2B3IdxTagValidB0B1B2B3 01919911231182413A005189 1150––––92D0–––– 21B100020408A2D19315DA3B 3360––––B0B0–––– 4321436D8F09C120–––– 50D13672F01DD16104963415 6310––––E13183771BD3 716111C2DF03F140––––

33. – 33 – CS 105 Address Translation Example #1 Virtual Address 0x03D4 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address CO ______CI___CT ____Hit? __Byte: ____ VPO VPN TLBI TLBT 131211109876543210 PPOPPN CO CICT 11109876543210 0000111 10 10100 0F303YN0D 001101010100 05 Y36

34. – 34 – CS 105 Address Translation Example #2 Virtual Address 0x028F VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address CO ______CI___CT ____Hit? __Byte: ____ VPO VPN TLBI TLBT 131211109876543210 PPOPPN CO CICT 11109876543210 0000101 00 01111 0A202NN09 001001001111 33 N??

35. – 35 – CS 105 Address Translation Example #3 Virtual Address 0x0040 VPN ___TLBI ___TLBT ____TLB Hit? __Page Fault? __PPN: ____ Physical Address CO ______CI___CT ____Hit? __Byte: ____ VPO VPN TLBI TLBT 131211109876543210 PPOPPN CO CICT 11109876543210 0000000 10 00000 01100NY —

36. – 36 – CS 105 Multi-Level Page Tables Given: 4KB (2 12 ) page size 32-bit address space 4-byte PTEProblem: Would need a 4 MB page table! 2 20 *4 bytes Per-process Common solution Multi-level page tables E.g., 2-level table (Pentium) Level-1 table: 1024 entries, each of which points to a Level 2 page table. Level-2 table: 1024 entries, each of which points to a page Level 1 Table... Level 2 Tables

37. – 37 – CS 105 Main Themes Programmer’s View Large “flat” address space Can allocate large blocks of contiguous addresses Process “owns” machine Has private address space Unaffected by behavior of other processes System View User virtual address space created by mapping to set of pages Need not be contiguous Allocated dynamically Enforce protection during address translation OS manages many processes simultaneously Continually switching among processes Especially when one must wait for resource »E.g., disk I/O to handle page fault