1. Design of a 8-bit RISC Micro controller Core By Ayush Mittal(200105011) Rakesh Kumar Sahoo(200105059) Under Guidance of Dr. M.B.Srinivas

2. Project Goal A 8-bit RISC micro controller to meet the requirements of low cost embedded Applications is designed.This particular micro controller core has been designed with 256 word of program memory and 128 bytes of data memory.Each instruction word is of size 14 bits.

3. Where to start? Shall I start ALU ? or Control Unit ? or Program counter ? Lets start from the scratch…………………

4. Brief overview: First step towards designing a microprocessor is selecting the instruction set. one can select his own instruction set or can use already existing instruction set. We have chosen PIC micro controller ISA. Next step in design process is dividing the instruction set into different categories such as 1.register type 2.branch type 3.jump type in our case we have only 2 type of instruction: register type and jump type. Next step is to draw the block diagram of the processor with all the components.

5. Once block diagram is ready,all we need is to design the individual components in the following sequence 1.ALU 2.Program memory and Data memory 3.control Unit Finally the tristate registers and MUX’s and DMUX’s.

6. Instruction format :

7. Instruction set: Type of Instruction: Register type- –In this type of instruction the operation of the processor is between registers. –As in the RISC core the instruction contains the immediate data. So an immediate operand instruction can also be considered to be a register type instruction with data in instruction register. –Also here we have all the data stored into program memory so memory access instructions can be considered as register type.

8. Jump type –There is only one instruction in this category – GOTO instruction. –This instruction is used to branch to any location unconditionally.

10. Block Diagram:

11. Division of design: The design is divided into following components for modularity and finally all the components are combined. 1. PC (program counter) 2. Program memory 3. Instruction register 4. File Register 5. ALU 6. Control unit 7. ALU control unit 8. Status Register 9. 2to1 MUX (8 bit wide) 10. Tristate register We will discuss design of each individual component and then combine all the components to reach at final design.

12. Registers and Memory: Instruction Register –It’s a 14 bit register which takes input from program memory. –It gives 6 bit op-code to control register. –It gives 7 bit address of file register. –It gives 8 bits immediate literal for GOTO instr. File Register Program memory –It’s a 256 x 14 bit memory. –It has 8 bit address bus. –It’s a 128 x 8 bit register array. –It has 7 bit address bus. –It is one of the input’s of ALU. W-register –It’s a 8 bit tri-state register. –It is used to store the output of ALU operation.

13. Status Register –It’s a 3 bit register used to store status of ALU operations like Carry(C), Auxiliary Carry(AC) & Zero(Z). –It is controlled by signal called PSW write. Program Counter –It is a 8 bit register it contains the address of next instruction in the Program Memory. –It is incremented by 1 after every instruction.

14. Design of ALU: This is a 8- bit ALU which performs the following operations - ADD, SUBTRACT, OR, XOR, AND, INCREMENT, DECREMENT, etc. ALU uses flag register(f – reg.) and working register(w – reg.) for its input and output. It is a purely combinational circuit. The inputs are multiplexed and one mux selects between B- reg. and PC. The other mux selects between W- reg. and immediate byte. The output is de-multiplexed between File Register and W- reg. or the output is multiplexed separately with Instruction Memory to store next value of PC.

15. B- reg. I/p W- reg. I/p ALU mode To PC File reg. or W-reg. I/P & O/P Connection to ALU:

16. Design of control unit: Control unit is a sequential state machine. In our design control unit completes one instruction in 4 clock cycles (except for jump instruction). These 4 steps are 1.instruction fetch step 2.instruction decode and register fetch step 3.execution and branch completion step 4.result store step.

17. pcwrite instrwr regwrit memread ipsel pcwrite alusrca alusrcb aluop dbit pswwrite wregsel pcsrc opcode Control unit block Diagram:

18. Reset Memread= 0 Alusrca=0 Alusrcb=1 Pcsrc=1 Pcwrite=1 Aluop=10 resetstart STATE DIAGRAM:

19. Instruction fetch Memread=1 Alusrca=0 Alusrcb=1 Pcsrc=1 Pcwrite=1 Aluop=10 Instr_decode0 Pcsrc=0 Pcwrite=1 Aluop=00 Instr_dec ode1 Ipsel=0 Aluop=00 Instr_de c_goto Ipsel=0 Aluop=0 0 s tart M SB=11 MSB=00/ 01 MSB=10 Start Instruction execute0 Instruction execute1

20. Alusrca= 1 Alusrcb= 0 Aluop=01 Instr_storew1 Wregsel=1 Aluop=00 Instr_storef1 Regwrite=1 Wregsel=0 Aluop=00 Dbit=0 Dbit=1 start

21. Instructio n store w0 Wregsel= 1 Aluop=00 Instruction store f0 Wregsel=0 Regwrite=1 Aluop=00 Instruction execute0 Dbit=0 Dbit=1 start

22. 1.instruction fetch step: IR= program_memory [PC]; PC=PC+1; During this clock cycle the instruction pointed by program counter is brought to instruction register. Also program counter is incremented by 1 so that it can point to next instruction to be fetched. 2.instruction decode and register fetch step: B= file_register [f]; The values read from register file may be needed at later stages, so we read it from register file and store it in the temporary register B for later use.

23. 3.execution and branch completion step: arithmetic and logical operation: ALU_OUT= A op W; Branch operation: If (A=W) PC=ALU_OUT; Jump operation: PC=ADDR; 4.Result store Step: file_register [f]= ALU_OUT

24. ALU Control:  It is a combinational unit that takes 5-bit input from instruction memory and a control input from control input.  It decodes the instruction from instruction memory and sends a 4 bit code to ALU for the type of operation it has to perform.  It is controlled by signal ‘aluop’ so that it gives instruction code to ALU only when ALU operation is required.

25. Limitations: There is no pipeline designed in the present design. Though it is based on the ISA of PIC micro controller all the instructions are not taken into consideration.In order to avoid complexity CALL instruction and the inbuilt timer and A/D converter is not designed in the present design.

26. Future advancement: 1.Pipeline can be implemented into the processor. 2.We can implement the other instructions like(CALL and RETURN). 3.Sorting algorithm can be hardwared into the processor for sorting the data stored in the file registers so that we can avoid delay involved in sorting through software.

27. References: 1.Computer Organisation and Design By David A. Patterson & John L. Hennessy 2. VHDL By Dougles L. Perry 3.VHDL By Skahill Web reference: www.microchip.com