1. 16 October, 2009ASET talk - S.S.Upadhya Electronics and DAQ system for INO-ICAL prototype detector (Presented by S.S.Upadhya, TIFR on behalf of INO collaboration) OBJECTIVE: Feasibility study of INO prototype detector of dimension 1m 3 ( glass RPC ) Which demanded Fast implementation of electronics to study its performance Outline of Talk:  Introduction  Electronics set up  Main Sections  Front End Electronics  Trigger logic  Back end Processing  Typical configuration & Modules developed  DAq. Software  Performance and results  VME transformation of DAQ

2. 16 October, 2009ASET talk - S.S.Upadhya2 Introduction to Glass Resistive Plate Chamber (RPC) Glass RPC is a gaseous detector- gas mixture flown at the atmospheric pressure -Electric field is applied across the glass electrodes. An ionizing charged particle traversing the gap initiates a streamer in the gas volume that results in a local discharge( limited to 0.1cm2) of the electrodes. The discharge induces an electrical signal on external pickup strips on both sides, orthogonal to each other, which can be used to record the location and time of ionization. The RPC can be operated in either in streamer mode or avalanche mode. Typical signal amplitude is about 100-200mV in streamer mode where as few mV in avalanche mode and its rise time is less than a nano Second. Signal is derived from a pick strip and common ground plane onto a twisted pair line of 100 ohm impedance.

3. 16 October, 2009ASET talk - S.S.Upadhya3 3 Construction of RPC Pickup strips 30mm 2 mm thick spacer Glass plates Resistive coating on the outer surfaces of glass Two 2 mm thick float Glass Separated by 2 mm spacer 2 mm Gas chamber

4. 16 October, 2009ASET talk - S.S.Upadhya4 Prototype Detector and Electronics Informations to be recorded on every valid trigger : (Few per min)  Event time up to micro secs (RTC)  Particle interaction tracks (boolean status of X-Y pick-up signal in each layer) 768 bits  relative time of interaction along the layers(X-Y planes) of RPCs (24 TDCstops) Detector Specifications: 12 layers of RPCs RPC has X & Y-planes (orthogonal strips) Each plane gives 32 pick up signals Total no. of channels = 12x2x32 = 768 X=1m Y=1m Z=1m RTC Final Trigger INO controller TDC Readout Mod. Monitor Scaler CAMAC Controller CAMAC back end Front end Electronics DETECTOR RPC 60mm iron Design Considerations: Flexibility and scalability Fast implementation using available resources and expertise Custom design standard at front end and CAMAC standard at back end with a serial transfer of data

5. 16 October, 2009ASET talk - S.S.Upadhya5 Electronics Set up User configurable Daisy chain : an i nterface between Front end and Back end electronics for control, data transfer and monitoring Event daisy chain : 1 each for X & Y planes of 12 layers [T,E/-M,Ad(4),SD,Clk] Monitor daisy chain: 12 no.s ( 1each for 2 consecutive layers in X & Y planes )[M,R,Clk] Note: MAX length of a daisy chain can be 16 modules due to 4 bit address CAMAC system SIGNAL ROUTERS Trigger & TDC Control – Data Monitoring TRIGGER Controller Read out TDC RTC Eve Scalers Mon Scalers CAMAC Controller Amplifier and Discriminator Processing and Monitoring Layer 1 (X) [EveID,MonID] Amplifier and Discriminator Processing and Monitoring Layer 12 (X) Front End Back End Processing and Monitoring Amplifier and Discriminator Layer 1 (Y) Processing and Monitoring Amplifier and Discriminator Layer 12 (Y)

6. 16 October, 2009ASET talk - S.S.Upadhya6 Main Sections of Electronics Front End Electronics Amplifier & Discriminator Processing and Monitoring Signal Routers Trigger logic Front end (Tigger-0 & 1) Back end (Final Trigger) Back end Processing Event process Monitor process

7. 16 October, 2009ASET talk - S.S.Upadhya7 Front end: Amplifier & Discriminators 8 channel Amplifier : RPCs in avalanche mode gives very small pulses of few mV and hence signal is amplified Specifications : placed close to pick-up strips a gain of 80 rise time of 2 ns Front End Discriminator: Converts the pickup signals over set threshold to digital signals (Diff ECL) Specifications: 16 channels per module common threshold variable from 2 to 500mV houses Trigger-0 logic also 1595+1513 1597+1513 AD96687

8. Amplifier output 16 October, 2009ASET talk - S.S.Upadhya8

9. 16 October, 2009ASET talk - S.S.Upadhya9 Front End: Processing & Monitoring Translator and wave shaper (TTL & 400ns width) 48_bit Parallel to Bit Serial Event Register 2:1 MUX M fold coincidence (Trigger-1 logic ) CPLD Discriminator signals ( 32 Diff. ECL ) T0 signals from Discriminator T1 signals Board ID [8 bit] 40:1 MUX Eve & Mon Decoder 6_bit Counter (Mon Chnl Addr) 2:1 MUX Translator (LVDS to TTL) EveComMon Interface signals MClk MR MonEn EveEn Eve ID Mon ID EveClk SI SO clk Eve SI Mon SI Eve SO Mon SO Cal Freqs T load CPLD Translator (TTL to LVDS) EveComMon Interface signals INTERFACE SIGNALS EveCom (event daisy chain)  OUT : EveSO, EveClk, Addr(4), E/ nM,T  IN : EveSI, EveClk, Addr(4), E/ nM,T Mon :: (Monitor daisy chain)  OUT : MonSO, MClk, MR  IN : MonSI, MClk, MR 0ne per plane of RPC Registering track data and transfer serially Select a pick up signal for monitoring

10. 16 October, 2009ASET talk - S.S.Upadhya10 Sequence of Signals in Event and Monitoring process E / M First pulse after address enables the board for monitor Next channel selection EVENT READ OUT CYCLE: ADDR(4) Clk SO Monitor cycle ADDR(4) Board 0 Board 1 Board 0 MR Mclk MO E/ M

11. Captured Event data transfer of Layer 0 16 October, 2009ASET talk - S.S.Upadhya11 Bd ID

12. Captured event data transfer of layer 11 16 October, 2009ASET talk - S.S.Upadhya12

13. 16 October, 2009ASET talk - S.S.Upadhya13 Processing & Monitoring module Processing and Monitoring module: Latches Boolean status of 32 pick up signals and board ID, on a final trigger Transfers latched data over event daisy chain Select the channels for monitoring Generates M fold trigger –T1 per plane Board has board-ID, event-ID, monitoring-ID one per plane ie total of 24 modules XC 9536 Trigger-1 XC 95288 Processing & Monitoring Event (48 bit)=BdID(6)+F(4)+MCh(6)+Pickup(32)

14. 16 October, 2009ASET talk - S.S.Upadhya14 Front End:: Signal Routers Routing of like signals between Front end and Back end Trigger & TDC Router: Routes primitive Trigger signals and TDC stop signals from each front end Processing boards of RPC planes to Final TRIGGER module and TDC module at back end CAMAC Control & Data Router: Caters the control signals from INO controller at back end to all the front end Processor modules via daisy chains Routes serial event data and selected pick signals for monitoring from front end boards via respective daisy chains to Read out board and Monitor Scalers at back end.

15. 16 October, 2009ASET talk - S.S.Upadhya15 Trigger Logic (MxN fold) For X-planes in Front End Discriminator (FED) module [ TRIGGER 0 LOGIC - T0 trigger] Pickup signals crossing set threshold converted to DIGITAL (diff ECL) ; typical rate ~200Hz Every 8 th pickup signals in a plane are logically ORed to get T0 signals (S0 to S7) Sn rate is 4x200= 800Hz In Processing and Monitoring module [ TRIGGER 1 LOGIC - T1 trigger] M fold coincidence of S1 to S8 signals (equivalent to M fold coincidence of consecutive pickup signals in a plane)- 1F,2F,3F,4F Final Trigger Module ( CAMAC std. ) [ TRIGGER 2 LOGIC - T2 trigger ] M fold signals(1F,2F,3F,4F) from all the X-planes are the inputs (diff LVDS) MxN fold trigger is generated ie N fold coincidence of M fold (T1) triggers from consecutive planes typical MxN folds implemented are 1x5, 2x4, 3x3, 4x2 For Y-planes Similarly MxN fold for Y-plane is generated Final Trigger is logical OR of MxN fold trigger from X and Y-planes Final Trigger invokes DAq system via LAM to record the event information. BACK Eg: M = 1F :: S0+S1+….+S7 M = 2F :: S0.S1+S1.S2 + S2.S3 + S3.S4 + ….. + S7.S0 M = 3F :: S0.S1.S2+S1.S2.S3 + S2.S3.S4 + S3.S4.S5 + ….. + S7.S0.S1 M = 4F :: S0.S1.S2.S3+S1.S2.S3.S4 + S2.S3.S4.S5 + ….. + S7.S0.S1.S2

16. 16 October, 2009ASET talk - S.S.Upadhya16 Final Trigger Module Final Trigger Module: M folds of all X & Y planes are inputs Generates MxN folds - final trigger Final trigger invokes LAM Inputs and MxN outputs of trigger logic are individually mask-able. Counting of all triggers by built-in scalers Boolean status of M fold signals are latched on final trigger for later reading design is FPGA based

17. 16 October, 2009ASET talk - S.S.Upadhya17 Back end Processing:: Event and Monitor process Final Trigger Event Process Invokes LAM for Event process SW via INO controller initiates track data transfer serially to Read-out module Registers Track data in front end Event time,TDC data and Trigger rates at back end Registered Data is ready for reading into PC via CAMAC bus Monitor Process Periodic 1Hz Trigger from INO controller Register the counting rate of selected pick-up signal in Mon-Scaler Registered Data is ready for reading into PC via CAMAC bus

18. 16 October, 2009ASET talk - S.S.Upadhya18 INO Controller % n Mon LAM Mon MO SW MClk MR 10MHz % n Event Bit counter %48 Test Pattern(8) Module Address Counter(4) Eve Com 10MHz Event SW SO Clk T E/M Event process Monitor process

19. 16 October, 2009ASET talk - S.S.Upadhya19 INO Controller INO Controller: In Event process, SW initiates the Controller to flush data serially from all processing modules over event daisy chains. In Monitoring process, It selects the channels to be monitored. Event and monitoring parameters like event data transfer speed, data size, monitoring period etc. are user programmable via CAMAC interface SW controlled Diagnostic features for DAq. is supported.

20. 16 October, 2009ASET talk - S.S.Upadhya20 INO Controller Fig.6 INO Controller

21. 16 October, 2009ASET talk - S.S.Upadhya21 INO Readout Module EveCom and Mon interface signals Serial In Parallel Out Shift REG(16) clk Serial In Parallel Out Shift REG(16) clk Translator LVDS to diff ECL FIFO Buffer(16) FIFO Buffer(16) EveClk Mon MO (1 to 8) To Monitor Scalers CAMAC Function & Address Decoder CAMAC bus OF Event EveSO EveClk Event EveSO W W

22. 16 October, 2009ASET talk - S.S.Upadhya22 INO Readout Module Read-out Module: Receives Event data over 2 serial connections and 8 pick-up signals for monitoring from 8 monitor daisy chains. Serial Data converted into 16bit parallel data and stored temporarily in FIFOs buffer. program reads FIFO data via CAMAC interface 8 pickup signals are converted from LVDS to ECL for Scaler compaibility

23. 16 October, 2009ASET talk - S.S.Upadhya23 Typical configuration of Electronics Setup and DAq. System

24. 16 October, 2009ASET talk - S.S.Upadhya24 Scalability on demand (Eg. 1m to 4m RPC) X-plane Processing & Monitoing(48) Eve-Mon :: 00-03 Processing & Monitoing (48) Eve-Mon :: 01-07 Processing & Monitoing (48) Eve-Mon :: 02-03 Processing & Monitoing (48) Eve-Mon :: 10-03 Processing & Monitoing (48) Eve-Mon :: 11-07 Processing & Monitoing(48) Eve-Mon :: 00-02 Processing & Monitoing (48) Eve-Mon :: 01-06 Processing & Monitoing (48) Eve-Mon :: 02-02 Processing & Monitoing (48) Eve-Mon :: 10-02 Processing & Monitoing (48) Eve-Mon :: 11-06 Processing & Monitoing(48) Eve-Mon :: 00-01 Processing & Monitoing (48) Eve-Mon :: 01-05 Processing & Monitoing (48) Eve-Mon :: 02-01 Processing & Monitoing (48) Eve-Mon :: 10-01 Processing & Monitoing(48) Eve-Mon :: 11-05 Processing & Monitoing(48) Eve-Mon :: 00-00 Processing & Monitoing (48) Eve-Mon :: 01-01 Processing & Monitoing (48) Eve-Mon :: 02-00 Processing & Monitoing (48) Eve-Mon :: 10-00 Processing & Monitoing (48) Eve-Mon :: 11-01 Event chain Mon chain

25. Event data transfer for all 12 layers 16 October, 2009ASET talk - S.S.Upadhya25

26. 16 October, 2009ASET talk - S.S.Upadhya26 EVENT RECORDING On a Event process, program records  Event time up to microsecond  24 TDC readings  Boolean status of all pickup signals  Useful Trigger rates MONITORING On a periodic Monitoring trigger ( 1Hz)  Monitor time recorded up to microsecond  Rates of selected set of channels are recorded  Next set of channels are selected for monitoring DAq. Software DAq. Program has been developed in C under Linux Main program displays Event data, Monitor Data as well it responds to user Key hit services

27. 16 October, 2009ASET talk - S.S.Upadhya27 BACK DAq. Software SW & HW initialization Enable LAM Handler Any Key Key Hit Services Execute Services Quit Y N N Y STOP Main program Display Event and Monitor Data RETURN Read LAM Register Event Flag. Initiate data transfer from front end to Read-out module. Record RTC time, TDC, Event Scaler. Record Read-out module data. Write data to file Monitor Flag. Record RTC time. Record Monitor scalers. Select next set of channels. Clear Monitor scalers N N Y Y LAM Handler Program control On LAM

28. 16 October, 2009ASET talk - S.S.Upadhya28 Home made Modules population in the setup RPC Y plane RPC X plane RPC Y plane INO CONTROLLER INO READOUT TRIGGER C&D ROUTER T&T ROUTER 48 24 12 TOTAL=173 modules

29. 16 October, 2009ASET talk - S.S.Upadhya29 Electronics and DAq. System RPC Detector Back end Electronics Front End Electronics BACK

30. 16 October, 2009ASET talk - S.S.Upadhya30

31. 16 October, 2009ASET talk - S.S.Upadhya31 Modules Developed in-house Processing and Monitoring module: Latches Boolean status of 32 pick up signals and Board ID on a final trigger Transfers latched data over event daisy chain Select the channels for monitoring Generates M fold trigger –T1 per plane Board has data-ID, event-ID, monitoring-ID one per plane ie total of 28 modules Final Trigger Module: M folds of all X & Y planes are inputs Generates MxN folds and final trigger Final trigger invokes LAM Inputs and outputs of trigger logic are individually mask-able. Counting of all triggers by built-in scalers Boolean status of M fold signals are latched on final trigger for later reading design is FPGA based

32. 16 October, 2009ASET talk - S.S.Upadhya32 Control and Data Router: Routes the control signals from controller to processing modules in the daisy chain. Routes latched event data serially and monitor signals from processing modules to back end via daisy chains Trigger and TDC Router: Routes M fold signals from all the processing modules to Final Trigger modules Routes 1F signals from each processing module to TDC module as TDC stops

33. 16 October, 2009ASET talk - S.S.Upadhya33 INO Controller: In Event process, SW initiates the Controller to flush data serially from all processing modules over event daisy chains. In Monitoring process, It selects the channels to be monitored. Event and monitoring parameters like event data transfer speed, data size, monitoring period etc. are user programmable via CAMAC interface Diagnostic features for DAq. is supported. Read-out Module: Receives Event data over 2 serial connections and 8 pick-up signals for monitoring from respective chains. Serial Data converted into 16bit parallel data and stored temporarily in FIFOs buffer. program reads FIFO data via CAMAC interface BACK

34. 16 October, 2009ASET talk - S.S.Upadhya34 Performance and Conclusion  Most of the relevant modules are fabricated in-house and integrated into the system.  The Electronic set up in conjunction with the prototype detector has been performing satisfactorily.  Serial data transfer is tested upto a baud rate of 1 Mbps.

35. 16 October, 2009ASET talk - S.S.Upadhya35 Some interesting cosmic ray tracks

36. 16 October, 2009ASET talk - S.S.Upadhya36 BACK

37. 16 October, 2009ASET talk - S.S.Upadhya37 Discriminator performance – RPC pulse profile

38. 16 October, 2009ASET talk - S.S.Upadhya38 Histogram of Noise rate of pickup Chnl, Cal & Fold

39. 16 October, 2009ASET talk - S.S.Upadhya39 Avg Noise rate Monitor plot over days

40. 16 October, 2009ASET talk - S.S.Upadhya40 Histogram of Avg Noise rate over days

41. 16 October, 2009ASET talk - S.S.Upadhya41 Typical TDC distribution of a pickup plane

42. 16 October, 2009ASET talk - S.S.Upadhya42 Width matches with pick-up strip width of 28mm

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44. 16 October, 2009ASET talk - S.S.Upadhya44

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46. 16 October, 2009ASET talk - S.S.Upadhya46 Change over of back end Electronics ( CAMAC to VME ) NECESSITY TO CHANGEOVER: Demerits of CAMAC: Low bus speed of 3MBps as well as large deadtime leading to few Hz trigger rate capability Limitations of scalability to large number of channels and synchronous bus cycles As a road map to support millions of channels of information in upcoming INO-ICAL experiment, it has been decided to convert Back-end to VME based DAQ. Building of VME Hardware expertise in house Picked up commercial modules wherever possible Development of customized modules equivalent to the in-house developed modules in CAMAC system, using VME based general purpose FPGA modules Development of user friendly DAQ programs and Analysis tools to groom Software expertise to with stand SW challenges ahead in the INO experiment

47. 16 October, 2009ASET talk - S.S.Upadhya47 Introduction to VME (VERSA-Module Eurocard)

48. 16 October, 2009ASET talk - S.S.Upadhya48 VME BASED DAQ SETUP X strip signals Y strip signals Timing info Digital Front End Analog Front End Trigger Module Event Trigger Event/ Monitor Data VME CRATE Scaler TDC Controller & Readout Module Linux based DAQ software (C++, Qt, ROOT) Interrupt Based Multi-Threaded Graphical User Interface Online 2D/3D Event Display RPC Strip Monitoring Online Error Reporting RPC Stack Final Trigger

49. 16 October, 2009ASET talk - S.S.Upadhya49 VME at a glance VME crate (chassis) smart fan units VME masterVME slaves power supply backplane Scaler TDC Latch Front End Controller & Readout Trigger generator

50. 16 October, 2009ASET talk - S.S.Upadhya50 The standards: summary

51. 16 October, 2009ASET talk - S.S.Upadhya51 INO team at RPC lab Thank you

52. 16 October, 2009ASET talk - S.S.Upadhya52 VME Mechanics 3U P1 160 x 100 mm P0 6U P1 P2 160 x 233 mm P1 P0 P2 P3 P4 J1/P1 DIN 96 pins 3 rows x 32 J1/P1 & J2/P2 DIN 160 pins 5 rows x 32 J0/P0 J4/P4 metric 95 pins 5+2 rows x 19 (2 mm) J5/P5 metric 110 pins J6/P6 metric 125 pins VME64XP 9U P1 P0 P2 P5 P4 P6 367 X 400 mm

53. 16 October, 2009ASET talk - S.S.Upadhya53 VME protocol

54. 16 October, 2009ASET talk - S.S.Upadhya54 Single Cycle (Read) Transfer speed: 4 MByte/s Valid Address Valid AM Valid Data ADDR AM /WRITE /AS /DS0, /DS1 /DTACK DATA Next Address Next AM master requests data master gets data master anticipates new address master validates address master starts a new cycle slave validates data end of 4 edge handshake

55. 16 October, 2009ASET talk - S.S.Upadhya55 Single Cycle (Write) Transfer speed: 4 MByte/s ADDR AM /WRITE /AS /DS0, /DS1 /DTACK DATA master releases data slave gets data end of 4 edge handshake master validates address and data Valid Address Valid AM Valid Data Next Address Next AM Next Data

56. 16 October, 2009ASET talk - S.S.Upadhya56 BLT Cycle (Read) Transfer speed: 40 MByte/s Valid Address Valid AM Valid Data ADDR AM /WRITE /AS /DS0, /DS1 /DTACK DATA master gets data master validates address slave validates data Valid Data slave latches address Valid Data N cycles master closes BLT cycle master can release address end of handshake slave increment address counter

57. 16 October, 2009ASET talk - S.S.Upadhya57 MBLT Cycle (Read) Transfer speed: 80 MByte/s ADDR AM /WRITE /AS /DS0, /DS1 /DTACK DATA master validates address Address acknowledge Valid Data slave latches address Valid Data Valid Address Valid AM Valid Address address bus direction changes master gets data N cycles master requests data

58. 16 October, 2009ASET talk - S.S.Upadhya58 Double edge transfers Valid Data ADDR/DATA /DS0, /DS1 /DTACK MBLT 1 edge transfer 4 edge handshake 80 MB/s ADDR/DATA /DS0, /DS1 /DTACK Valid Data 2eVME 2 edge transfer 2 edge handshake 160 MB/s ADDR/DATA /DS0, /DS1 /DTACK Valid Data 2eSST 2 edge transfer no handshake 320 MB/s DS used only to start cycle transmitter throttles data: source synchronous transfer

59. 16 October, 2009ASET talk - S.S.Upadhya59 VME bus

60. 16 October, 2009ASET talk - S.S.Upadhya60 Team behind success Prof. N K Mondal, Prof. B S Acharya, B Satyanarayana S.S.Upadhya, S.D. Kalmani, Anitha Behere (BARC), B.K.Nagesh, Mandar Sharaf, Shobha K.Rao, K.K.Rao, L.V. Reddy, Shinde Shekar, Manas, S.R.Joshi VME transformation: THANK YOU ONE & ALL

61. 16 October, 2009ASET talk - S.S.Upadhya61 Electronics and Data Acquisition system for prototype INO-ICAL detector S.S.Upadhya, TIFR ( on behalf of INO collaboration ) OBJECTIVES: Feasibility study of INO prototype detector ( RPC ) of dimension 1m 3 Fast development of electronics to study the detector performance Outline of Talk:  Introduction  Experimental set up  Front end Analog Electronics  Trigger logic  Software  Typical Electronics setup and DAq. System  Modules developed in-house  Performance and Conclusion OBJECTIVES: Feasibility study of INO prototype detector ( RPC ) of dimension 1m 3 Fast development of electronics to study the detector performance Outline of Talk:  Introduction  Experimental set up  Front end Analog Electronics  Trigger logic  Software  Typical Electronics setup and DAq. System  Modules developed in-house  Performance and Conclusion

62. 16 October, 2009ASET talk - S.S.Upadhya62 INO Detector Concept Resistive Plate Chambers (RPC) Magnetised Iron

63. 16 October, 2009ASET talk - S.S.Upadhya63 Largest Basic Science Project in the country No of modules 3 Module dimension 16 m X 16 m X 12 m Detector dimension 48 m X 16 m X 12 m No of layers 140 Iron plate thickness 6 cm Gap for RPC trays 2.5 cm Magnetic field 1.5 Tesla RPC unit dimension 2 m X 2 m Readout strip width 2 cm No. of RPCs/Road/Layer 8 No. of Roads/Layer/Module 8 No. of RPC units/Layer 192 Total no of RPC units 27000 No of Electronic channels 3.6 X 10 6

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