1. A preliminary approach to the needs of open loop control of the Lorentz Force Detuning is to generate a custom piezo control signal with proper and tunable shape and timing (referred to a master sync input signal). A simple and low chip-area consuming FPGA algorithm that handle such issue has been implemented. Abstrac t A coaxial (blade) tuner solution has been developed for the compensation of the Lorentz force detuning of the superconducting cavities under the high gradient pulsed operation foreseen for ILC operation. The device is based on prototypes successfully tested at DESY in 2002 both on CHECHIA and on the superstructures inserted in the TTF string. An improvement of the tuner characteristics has now been designed by the integration of fast tuning capabilities by means of piezo-ceramic element. Two prototypes of the new INFN coaxial piezo blade tuner have been manufactured and will be tested in the near future at DESY and BESSY after integration with the cavities. Meanwhile also the control electronics is under developing based on a FPGA electronic platform, a SIMCON 3.1 board from DESY LLRF group led by S. Simrock. Once completed it will allow to implement a first prototype of a complete blade tuner control system. Here the blade tuner design and its main characteristics are presented, together with the latest results from the activity on electronics. CAS course "Introduction to Accelerator Physics" – Zakopane, Poland, 1 – 13 October 2006 Piezo system: Recently, a fast, piezo-based, tuning action has been added to the blade tuner concept. In the picture it’s possible to see the piezoelectric elements acting between the ring-blade assembly and the outer ring. The piezo actuators provide fast tuning capabilities needed for Lorentz Force Detuning (LFD) compensation and microphonics stabilization. Two complete prototypes, including He tanks and piezo actuators, have been manufactured. Tests were initially foreseen on summer 2006 at DESY and BESSY after the final tuner integration with two existing TTF cavities, but higher priorities for the Module 6 assembly operation at DESY lead to a delay in the testing program. The movement leverage: Two existing blade tuner assemblies have been equipped with a revised leverage system. With respect to the original system used for the TTF superstructures, the leverage system has been rotated to one side, in order to avoid the mechanical interferences with the Invar rod providing the cavity longitudinal alignment in the TTF CRY3 design. The threaded bars: The four threaded bars, parallel to the piezo elements accomplish two different tasks: first of all they are needed during transportation, handling and assembly phases to avoid inelastic deformations of the bellow. In this case they are tightly bolted at both ends to provide stiffness to the system. Furthermore, in the operating condition, the inner bolts are loosened by few hundredths of mm and the bars act as safety devices in case of piezo mechanical failure or overpressure conditions inside the Helium tank Modified Helium tank: Because the tuner is fixed to the helium tank, a bellow is needed between the two fixed rings. The position of pad supports has been reviewed in order to minimize the bending forces on the helium tank bellow and, of course, on piezo elements. The bending rings: The ring-blade assembly, consists of three different rings: one of the external rings is rigidly connected to the helium tank, while the central one is symmetrically divided in two halves. The central arm is connected to the bending system to produce the right rotation and the correct axial movement for the tuning. The rings are connected by thin titanium plates (blades) that can change the cavity length (compression and tension) as a results of an azimuthally rotation in opposite direction of the two halves of the central ring. The Closed Loop stage could instead be forced to implement, for the sake of stability and performance of the loop, a digital filter with detailed transfer function, both in amplitude and phase. Then an algorithm has been developed for state-space computations FPGA implementation, in this particular case the design has been chosen in order to keep as low as possible the logic resources requested. SIMCON 3.1 board main features: single low latency PCB board, VME standard based 10 analog input channels, AD6645 ADC’s up to 105 MSPS, 14 bit 4 analog output channels, AD9772A DAC’s up to 160 MSPS, 14 bit XILINX Virtex II-Pro FPGA chip - main processing unit ALTERA ACEX FPGA chip - VME and Internal Interface interpreter State Space Order Maximum achievable sampling frequency [kHz] 6420 32100 16300 tunable delay from master sync custom shape and length of the pulse 10 s time resolution to build up the pulse pattern only 1% of chip logic resources needed up to 10 ms pulse length Courtesy of DESY LLRF group discrete state-space implementation 32 bit fixed-point computations 7% of chip logic resources needed Analog equipment: Phase detector Filter amplifier Piezoelectric actuator driver RF line (probe, delay etc.) Digital equipment: Fast ADC & DAC Signal processing stage (DSP or FPGA) Simulink schematic of State-Space algorithm Tuner control system schematic view: C. Pagani, A. Bosotti, P. Michelato, N. Panzeri, R. Paparella, P. Pierini INFN Milano - LASA, Italy