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EE3A1 Computer Hardware and Digital Design Lecture 2 Introduction to VHDL.

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1 EE3A1 Computer Hardware and Digital Design Lecture 2 Introduction to VHDL

2 Introduction  We’ll look at some simple design in VHDL  These will be the examples used in lab 1

3 A simple example  NAND gate  1 st thing to do:  Say what it looks like to the rest of the system  List of inputs and outputs  Port map

4 Port map: inputs and outputs  Uppercase is a VHDL keyword  Lower case is name I have chosen  Mode can be IN or OUT ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END;

5 Port map: inputs and outputs  Type STD_LOGIC can be ‘0’, ‘1’, ‘X’ or ‘U’.  ‘X’ means unknown  ‘U’ means uninitialized ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END;

6 Architecture ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END;  Now we know how many inputs and outputs  Next we say how outputs derive values from inputs:  Architecture

7 Architecture ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END;

8 Simulate it  Check our design by giving it inputs  Simulator says what the output would do Output is 0 when both inputs are 1: It works

9 Multiple architectures  We can give more than 1 architecture  Distinguish them by different names ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END; ARCHITECTURE complicated OF nandgate IS BEGIN c <= NOT ( a AND b ); END;

10 BEGIN and END statements C: Block defined by { and } for (i=1; i<=n; i++) { a[i]=i; b[i]=a[i]*a[i]; }  A block is a group of statements that should be treated as one

11 BEGIN and END statements VHDL: Block defined by BEGIN and END FOR i IN ( 1 TO N ) LOOP BEGIN a(i) = i; b(i) = a(i) * a(i); END LOOP;  A block is a group of statements that should be treated as one

12 Semicolons C: for (i=1; i<=n; i++); /* WRONG semicolon */ {; /* ALSO WRONG semicolon */ a[i]=i; b[i]=a[i]*a[i]; }  ; indicates end of statement.  Statements that "open up" a block don't take semicolons:

13 Semicolons VHDL: FOR i IN ( 1 TO N ) LOOP; --WRONG semicolon BEGIN; --ALSO WRONG semicolon a(i) = i; b(i) = a(i) * a(i); END LOOP;  ; indicates end of statement.  Statements that "open up" a block don't take semicolons:

14 ENTITY doesn’t need a BEGIN ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END;

15 Style issues  VHDL is not case sensitive.  In (black and white) books, VHDL keywords are normally in one particular case  In editors, VHDL keywords are normally in one particular colour

16 Style issues  These are the same: ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END; entity NANDGATE is port ( A, B: in std_logic; C: out std_logic); end; entity nandgate is port ( a, b: in std_logic; c: out std_logic); end;

17 Spaces, indents and line breaks  Have no effect on code meaning  Used to enhance clarity  These are the same: ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END; ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END;

18 Annotating END statements ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END;  It’s good style to say what you are ENDing

19 Annotating END statements  Often helps avoid bugs or confusion  Usually optional ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END ARCHITECTURE simple;  It’s good style to say what you are ENDing

20 Comments  Comments are introduced by two dashes -- This is a comment

21 Libraries void main () { printf(“My first C program”); }  ERROR: printf not found

22 Libraries #include void main () { printf(“My first C program”); }  Works OK

23 The IEEE library ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END ENTITY nandgate; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END ARCHITECTURE simple; u Error message “Cannot recognise type STD_LOGIC”.

24 Opening libraries  Definition of STD_LOGIC is held in library  Must open library in order to get at definitions  Main library is called IEEE LIBRARY IEEE; USE IEEE.XXXX.YYYY  XXXX is sub-library (package)  YYYY is feature that you want to use.

25 Opening libraries  Definition of STD_LOGIC is held in library  Must open library in order to get at definitions  Main library is called IEEE LIBRARY IEEE; USE IEEE.XXXX.ALL  If you want to open all features of the package

26 Using STD_LOGIC LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END ENTITY nandgate; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END ARCHITECTURE simple;

27 Questions What is the block diagram for this entity declaration? ENTITY question1 IS PORT ( a: IN STD_LOGIC; b: OUT STD_LOGIC; c: IN STD_LOGIC; d: OUT STD_LOGIC ); END ENTITY question1; What is wrong with this architecture (2 problems)? ARCHITECTURE simple OF question1 IS BEGIN b <= a NAND c; END ARCHITECTURE complicated;

28 What is the block diagram for this entity declaration? ENTITY question1 IS PORT ( a: IN STD_LOGIC; b: OUT STD_LOGIC; c: IN STD_LOGIC; d: OUT STD_LOGIC ); END ENTITY question1;

29 Questions  What is wrong with this architecture? ARCHITECTURE simple OF question1 IS BEGIN b <= a NAND c; END ARCHITECTURE complicated; Output d is never assigned a value Mismatch in architecture names

30 Example 2  Arithmetic Logic Unit  Heart of a microprocessor  1 st part of the assignment  To build ALU we need u Conditionals u Signals that are many bits wide u Arithmetic on signals

31 Conditionals LIBRARY ieee; USE ieee.std_logic_1164.ALL;

32 Conditionals LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY equals IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END ENTITY equals;

33 Conditionals LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY equals IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END ENTITY equals; ARCHITECTURE number1 OF equals IS BEGIN c <= '1' WHEN a=b ELSE '0'; END ARCHITECTURE number1;

34 Signals that are more than 1 bit  STD_LOGIC_VECTOR(0 TO 3)  Four members a(0), a(1), a(2) and a(3).  Each is of type STD_LOGIC.

35 Example of 4-bit device LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY orgate IS PORT ( a, b: IN STD_LOGIC_VECTOR(0 TO 3); c: OUT STD_LOGIC_VECTOR(0 TO 3)); END ENTITY orgate;

36 Example of 4-bit device ARCHITECTURE number1 OF orgate IS BEGIN C(0) <= a(0) OR b(0); C(1) <= a(1) OR b(1); C(2) <= a(2) OR b(2); C(3) <= a(3) OR b(3); END ARCHITECTURE number1;

37 Example of 4-bit device ARCHITECTURE number2 OF orgate IS BEGIN c <= a OR b; END ARCHITECTURE number2;  The compiler can figure out that a,b,c are 4 bits wide

38 Example of 4-bit device ARCHITECTURE number3 OF orgate IS BEGIN C(0 TO 3) <= a(0 TO 3) OR b(0 TO 3); END ARCHITECTURE number3;  Making the loop explicit

39 STD_LOGIC_VECTOR values  Single bit STD_LOGIC assignment:  a <= ‘1’;--single quotes  4-bit STD_LOGIC_VECTOR assignment:  a <= “1110”;-- double quotes.

40 Direction of numbering  Can number upwards or downwards  Both represent the same decimal number u 14 if it’s signed; -2 if it’s unsigned

41 Direction of numbering  In digital logic design bit 0 is usually lsb  So in VHDL index usually counts downwards

42 Arithmetic on STD_LOGIC_VECTOR s  Comparator  g b ELSE ‘0’;  Signed or unsigned? u 1111 is +15 or –1? u 1110 is +14 or –2?

43 Arithmetic on STD_LOGIC_VECTOR s  VHDL has two different versions of +,-,>,< etc. u STD_LOGIC_SIGNED u STD_LOGIC_UNSIGNED  Import one or the other

44 Arithmetic on STD_LOGIC_VECTOR s LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_signed.ALL; ENTITY comp IS PORT ( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); g: OUT STD_LOGIC); END ENTITY comp; ARCHITECTURE simple OF comp IS BEGIN g b ELSE ‘0’; END ARCHITECTURE simple; 1111 will be interpreted as -1

45 Arithmetic on STD_LOGIC_VECTOR s LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY comp IS PORT ( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); g: OUT STD_LOGIC); END ENTITY comp; ARCHITECTURE simple OF comp IS BEGIN g b ELSE ‘0’; END ARCHITECTURE simple; 1111 will be interpreted as 15

46 ALU example OpcodeOperation 00a + b 01a – b 10a and b 11a or b  16 bit ALU  Operation is selected by opcode

47 ALU example LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_signed.ALL; ENTITY alu IS PORT ( a, b: IN STD_LOGIC_VECTOR(15 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR(1 DOWNTO 0); c: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END ENTITY alu;

48 ALU example ARCHITECTURE simple OF alu IS BEGIN c <= a + b WHEN opcode=”00” ELSE a - b WHEN opcode=”01” ELSE a OR b WHEN opcode=”10” ELSE a AND b WHEN opcode=”11”; END ARCHITECTURE simple;

49 Simulate the ALU  a = “0000000001110111”, 0077H.  b = “0000000000000001”, 0001H.  As opcode changes “00”,”01”,”10”,”11”, (0,1,2,3)  output gets a+b, then a-b, then a OR b then a AND c.

50 Synthesise the example  It works as expected  Synthesise to gate level description  Much quicker and easier than doing it the old fashioned way  More flexible too

51 Summary  Intro to VHDL  Basic examples for use in lab 1

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