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L0 DAQ S.Brisbane. ECS DAQ Basics The ECS is the top level under which sits the DCS and DAQ DCS must be in READY state before trying to use the DAQ system.

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Presentation on theme: "L0 DAQ S.Brisbane. ECS DAQ Basics The ECS is the top level under which sits the DCS and DAQ DCS must be in READY state before trying to use the DAQ system."— Presentation transcript:

1 L0 DAQ S.Brisbane

2 ECS DAQ Basics The ECS is the top level under which sits the DCS and DAQ DCS must be in READY state before trying to use the DAQ system The DAQ is the section which looks after the configuration of the detector for data taking (rather than power up) The L1 and L0 are part of DAQ and must be configured correctly to take data –Configuration can be different for different purposes –The L0 configuration can vary from one board to the next, or between RUN_MODEs It is the job of the DAQ FSM to simply handle configuration for these different RUN_MODEs –Simplest example High granularity mode of the PIXEL chips (ALICE), or Normal granularity mode (LHCb) One example is the “PHYSICS” mode, we use this most often in commissioning

3 DAQ basics continued STATES –The L0 and L1 FSM can only be in the following predefined states NOT_READYNOT_READY – we normal state at power up CONFIGURING – State change in progress, can take some time READY – The L0 and L1 are configured for data taking RUNNING – the L0 and L1 are told to read out data ERROR – Something has happened ACTIONS –To configure a board/set of boards for data taking, use CONFIGURE –To start taking data, START –To stop data taking STOP –Before switching off the low voltage, RESET the L0 boards –If there is an ERROR, try to RECOVER

4 Configuring the L0 -What happens A-SideC-Side SPECS Communication L0 Boards + HPDs SPECS SLAVES JTAG to the L0’s PVSS Controls project FSM DNS server 1 DIM server per column, running on PC to which column is connected SPECS MASTER port on one of the PCS SPECS Slave on Column INSIDE the PC ALICE|TESTPULSE Recipe database Load And apply Communication via DIM

5 L0 Board + HPD Basics - explanation for last slide L0 board and HPD sit on detector They are the first pieces of electronics to see data There are many registers to set on the HPD and L0 boards before it is ready to take data. The parameters are stored in recipes. –Loading recipes and applying to L0 boards is handled by the an external PVSS component The configuration is performed from control PCS which are connected up remotely to each other and to the ECS system itself PVSS and 2 types of SPECS server run on the L0 control PCs –PVSS communicates via DIM to these servers in order to configure the system The SPECS protocol is used to send the configuration messages over long distances to the detectors At the column level, SPECS is translated to JTAG which is used for short distances

6 On the L0 controls PCs SPECS master boards perform the slow control configuration and monitoring for : A-side* : r2daq02w C-side* : r2daq01w U-Panel : r1daq01w D-Panel : r1daq02w Communication with masters provided by One L0 Dim Server per column One Specs server per PC DNS handles the pvss to server communications A PVSS project running on r2daq02w and r1daq01w * A8 runs from PC r2daq01w Installed as services Use Service+ to view

7 Level-0 FSM From the top level FSM, L0 can also be configured Status of each of the DIM servers is displayed underneath Red indicates server not running Status of each of the L0 boards is displayed using the RICH L0 summary panel, also available from the g:/rich/oper folder For LHCb shifter: During running, only Errors which make stopping a run necessary will be displayed here The RICH shifter cares in more detail….

8 RICH L0 Summary panel 8 L0 Boards Summary of HPDs and boards with corrupted registers is displayed with the RICHL0_Summary panel Shifters should check every few hours Detail of the error type is gained by clicking on the board in question Reconfiguring of single boards also possible this way Error information and recording for the RICH shifter FSMConfDB objects handle configuration recipes for different run modes

9 Other indications Striped pattern in the online monitoring – indicates L1 is getting bad data from a HPD Happens often during or after HV ramping Error not necessarily seen in FSM or summary panel Follow power cycling procedure on previous slide Please write in logbook

10 Errors incurred with HV Individual board errors during configuration are displayed in the FSM and summary panel Individual board errors incurred during run are displayed only in the summary panel Record the error (in logbook) and type (from summary panel) First, try to reconfigure a board in error If this fails –Switch it OFF from DCS for 5 seconds and back on again, reconfigure Power cycle the column from DCS, reconfigure. If the board is still in error, always exclude it from the FSM tree –Makes life easier to see other errors. –In final case – excluded boards must be reported to us

11 End RUN –Recommend you to RESET and CONFIGURE all L0 boards During a run, only errors serious enough to warrant the run to be stopped are displayed –Some register corruption may still have occurred resulting in reduced data quality End RUN procedure


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