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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 Arne Wall Institute MD, University of Rostock
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Agenda Optimization of Filter architecture Metric of VHDL-Synthesis Optimization of ST65-Synthesis Result Outlook
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Optimization of Filter architecture - Adder Use Carry-save adders for summation of partial products Use Carry-save adders for adder chain => only two Full adders of depth Last sum of sum vector and carry vector needs to be calculated fast
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Optimization of Filter architecture - Adder Adder Adders Register Partial products Previous Adders Register
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Metric of VHDL-Synthesis Frequency f [MHz]233 Area A [# of LUT-FF-Pairs]955 # of Pipeline Stages2 Metric [MHz^3]9.86 # Slice LUTs1275 # Slice Registers1006
![Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Metric of VHDL-Synthesis Frequency f [MHz]233 Area A [# of LUT-FF-Pairs]955 # of Pipeline Stages2 Metric [MHz^3]9.86 # Slice LUTs1275 # Slice Registers1006](http://images.slideplayer.com/26/8696623/slides/slide_5.jpg "Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Metric of VHDL-Synthesis Frequency f [MHz]233 Area A [# of LUT-FF-Pairs]955 # of Pipeline Stages2 Metric [MHz^3]9.86 # Slice LUTs1275 # Slice Registers1006")
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Optimization of ST65-Synthesis Metric [10^9*MHz^3/mW^2] Operating Voltage 1.01.11.21.3 Low V T --0.430.48 Medium V T --2.892.60 High V T 7.729.159.098.55
![Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Optimization of ST65-Synthesis Metric [10^9*MHz^3/mW^2] Operating Voltage Low V T Medium V T High V T](http://images.slideplayer.com/26/8696623/slides/slide_6.jpg "Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Optimization of ST65-Synthesis Metric [10^9*MHz^3/mW^2] Operating Voltage Low V T Medium V T High V T")
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Optimization of ST65-Synthesis Maximum Frequency [MHz] Operating Voltage 1.01.11.21.3 Low V T --565643 Medium V T --422491 High V T 147205264323
![Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Optimization of ST65-Synthesis Maximum Frequency [MHz] Operating Voltage Low V T Medium V T High V T](http://images.slideplayer.com/26/8696623/slides/slide_7.jpg "Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Optimization of ST65-Synthesis Maximum Frequency [MHz] Operating Voltage Low V T Medium V T High V T")
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Result Best Metric at 1.1 V Operating Voltage and High Threshold Voltage Frequency f [MHz]500 Area A [µm²]30.093 Power P_dyn [mW]16.41 Power P_leak [nW]229.85 # of Pipeline Stages2 Metric [10^9 MHz^3/mW^2]33.14
![Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Result Best Metric at 1.1 V Operating Voltage and High Threshold Voltage Frequency f [MHz]500 Area A [µm²] Power P_dyn [mW]16.41 Power P_leak [nW] # of Pipeline Stages2 Metric [10^9 MHz^3/mW^2]33.14](http://images.slideplayer.com/26/8696623/slides/slide_8.jpg "Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Result Best Metric at 1.1 V Operating Voltage and High Threshold Voltage Frequency f [MHz]500 Area A [µm²] Power P_dyn [mW]16.41 Power P_leak [nW] # of Pipeline Stages2 Metric [10^9 MHz^3/mW^2]33.14")
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 Result
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 10 Outlook Use fast Adder to add carry- and sum-vector Don’t use to much bits inside the multiplication Try further synthesis parameters
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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 11 Thank you for your attention!
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