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Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle.

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Presentation on theme: "Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle."— Presentation transcript:

1 Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conditional-Sum-Adder Conditional-Sum-Adder 4th Meeting: SYNOPSYS Peter Kröger, Peter Danielis Course and contest 2005

2 Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Optimization only for speed (frequency = 2000 MHz) Power and area only determined for last step Selected optionResult (adder_top) set_max_delay 0.0 -from all_inputs() -to all_outputs() compile –exact_map –map_effort high –ungroup_all Tools Design Optimization: More Map Options Incremental Mapping, Prioritize Min Paths Data arrival time: 1.01 ns MHz set_max_delay 0.0 –from all_inputs -to all_outputs() –incremental compile –exact_map –map_effort high –ungroup_all –incremental Tools Design Optimization: More Map Options Incremental Mapping Data arrival time: 0.96 ns MHz set_max_delay 0.0 –from all_inputs -to all_outputs() –incremental_mapping compile –exact_map –map_effort high –ungroup_all –incremental_mapping Data arrival time: 0.96 ns MHz Varying capacitance and fanout set_min_capacitance x1 all_inputs() all_outputs() set_max_capacitance x2 all_inputs() all_outputs() set_min_fanout y1 all_inputs() set_max_fanout y2 all_inputs()

3 Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Min. capacitanceMax. capacitanceMin. fanoutMax. fanoutData arrival time ns ns ns ns ns ns ns -1-1

4 Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization Selected optionResult (adder_top) set_resource_allocation constraint_driven set_resource_implementation constraint_driven Data arrival time: 1.47 ns 680,3 MHz set_ultra_optimization true -force set_resource_allocation constraint_driven set_resource_implementation constraint_driven set_flatten true -effort high -minimize single_output –flatten compile –exact_map –map_effort high –flatten Data arrival time: 1.03 ns 970,9 MHz set_ultra_optimization true -force set_flatten true -effort high -minimize single_output –area_effort none compile –exact_map –map_effort high –flatten –area_effort none Data arrival time: 0.96 ns MHz Multiple call of the compile-command compile_new_boolean_structure = true set_structure true –timing true –boolean true –boolean_effort high compile_use_fast_sequential_mode = true No improvement

5 Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Final results (Perhaps) Modification of the VHDL-File Other cells New structuring Data arrival time: 0,96 ns MHz Total dynamic power: mW Cell leakage power: mW Comb. area: square microns Outlook


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