1. Performed by: Guy Assedou Ofir Shimon Instructor: Yaniv Ben-Yitzhak המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Subject: Network On Chip Platform סמסטר אביב 2008 1

2. Abstract As today's technology advances rapidly and number of transistors implemented on single chip is ever growing, chip-manufacturers, in their endless efforts to increase performance, started integrating multiple processors on a single silicon chip. Official estimations suggest that in the near future we can expect to see tens of cores on a single chip. Traditionally, on-chip global communication between different cores has been addressed by shared- bus structures. However, current architecture cannot support estimated growth due to power, area, performance and parallelism considerations. In order to address communications within large VLSI systems implemented on a single silicon chip, a new paradigm emerged – Network on Chip. In a NoC system, modules such as processor cores, memories and DSP's exchange data using a network as a "public transportation". A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers). Thus, instead of one shared bus for all modules, communication is now distributed over a network. This new approach offers substantial benefits in comparison to bus architecture such as: Low power consumption, Parallelization, Scalability & Modularity and Speed optimization. On the other hand, NoC architecture has a few disadvantages: More complex to implement (over bus), Header penalty and Routing & reordering. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2

3. System description The NoC Platform is constructed from two main building blocks: CPU Module and Memory Module. The CPU Module is constructed from a Nios II core, an adaptor and a router. The adaptor translates Nios II core instructions, which are issued via bus ( “BUS language”), to packets which can be routed through the network (“NoC language”) and vice versa. The Memory Module translates packets into memory controller commands and returns the data requested to the correct destination in the platform (one of the CPU Modules). The system architecture is a shared memory architecture - one global memory which allows each core to see the entire memory space. Also, each core has its own private cache which can be accessed by only the core it is attached too. The platform is designed as a static routing platform meaning: –The route of each packet from one point to the other is permanent. –The order in which the packets are sent is the order in which the packets are received. The system was designed according to the following guidelines (order implies priority): –Keep it simple –Scalability & Modularity –Area –Performance המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware  Stratix II 60 FPGA  GIDEL ProcStar II 180 Board  Nios II Softcore  PC Software  Quartus II Development Environment  SoPC Builder  HDL Designer  ModelSim Logic Simulator  Nios II IDE  GIDEL PROCWizard 4

5. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5