1. Prof. Brian L. Evans PhD Students Karl Nieman, Marcel Nassar, and Jing Lin Department of Electrical and Computer Engineering The University of Texas at Austin Austin, TX May 6, 2013 Sponsored by National Instruments Academic Lead User Program FPGA Implementation of a Message-Passing OFDM Receiver for Impulsive Noise Channels

2. Outline Part I Smart grid communications Impulsive noise mitigation System design and implementation Part II Demonstration Part III Feedback for NI Next Steps 1 ISTOCKPHOTO.COM/© SIGAL SUHLER MORAN IEEE Signal Processing Magazine Special Issue on Signal Processing Techniques for the Smart Grid, September 2012. Background | System Design and Implementation | Demo | Conclusion

3. Local utility MV-LV transformer Smart meters Data concentrator Smart Grid Communications Home area data networks connect appliances, EV charger and smart meter via powerline or wireless links Smart meter communications between smart meters and data concentrator via powerline or wireless links Communication backhaul carries traffic between concentrator and utility on wired or wireless links 2 Low voltage (LV) under 1 kV Medium Voltage (MV) 1 kV – 33 kV Background | System Design and Implementation | Demo | Conclusion

4. Uses orthogonal frequency division multiplexing (OFDM) Communication challenges oCoChannel distortion oNoNon-Gaussian, impulsive noise Powerline Communications (PLC) CategoriesBandBit RatesCoverageEnablesStandards Narrowband 3-500 kHz up to 800 kbps Multi- kilometer Smart meter communication (ITU) PRIME, G3 ITU-T G.hnem IEEE P1901.2 Broadband 1.8-250 MHz up to 200 Mbps <1500 m Home area data networks HomePlug ITU-T G.hn IEEE P1901 3 Background | System Design and Implementation | Demo | Conclusion

5. Impulsive Noise in PLC 4 Outdoor medium-voltage line (St. Louis, MO) Cyclostationary noise becomes impulsive after interleaving Interleave Indoor low-voltage line (UT Campus) Background | System Design and Implementation | Demo | Conclusion

6. Impulsive Noise in OFDM Systems FFT spreads received impulsive noise across all FFT bins SNR of each FFT bin is decreased Receiver communication performance degrades 5 IFFTFilter + FFT Equalizer and detector Vector of symbol amplitudes (complex) Channel Receiver Background | System Design and Implementation | Demo | Conclusion

7. Impulsive Noise Mitigation (Denoising) 6 IFFTFilter ++ FFT Equalizer and detector Impulsive noise estimation Vector of symbol amplitudes (complex) + - Channel Receiver Background | System Design and Implementation | Demo | Conclusion

8. Approximate Message Passing (AMP) 7 Reconstruct time-domain noise from frequency- domain null tones Iterate until convergence Algorithm consists of: Mostly scalar arithmetic FFT/IFFTs Exponential Targeted at G3-PLC signaling structure Background | System Design and Implementation | Demo | Conclusion

9. Project Goals From theory to implementation: Understand computational requirements Determine real-time constraints in target application Find feasible solution Steps involved: Develop floating-point model and simulator Convert to fixed-point data and arithmetic Hardware/software partitioning Implementation 8 Background | System Design and Implementation | Demo | Conclusion

10. Mapping to Fixed-Point Variables sized using MATLAB Fixed-Point Toolbox Most variables sized to 16-bit wordlengths 9 Background | System Design and Implementation | Demo | Conclusion

11. AMP-Enhanced OFDM Testbed 10 RT controller LabVIEW RT data symbol generation FlexRIO FPGA Module 1 (G3TX) LabVIEW DSP Design Module data and reference symbol interleave reference symbol LUT 43.2 kSps 8.6 kSps zero padding (null tones) generate complex conjugate pair 103.6 kSps 256 IFFT w/ 22 CP insertion 368.3 kSps NI 5781 16-bit DAC 10 MSps RT controller LabVIEW RT BER/SNR calculation w/ and w/o AMP FlexRIO FPGA Module 2 (G3RX) LabVIEW DSP Design Module NI 5781 14-bit ADC sample rate conversion 10 MSps400 kSps time and frequency offset correction 400 kSps 256 FFT w/ 22 CP removal, noise injection 368.3 kSps FlexRIO FPGA Module 3 (AMPEQ) LabVIEW DSP Design Module null tone and active tone separation 184.2 kSps 51.8 kSps channel estimation/ ZF equalization AMP noise estimate Subtract noise estimate from active tones data and reference symbol de- interleave 51.8 kSps 8.6 kSps Host Computer LabVIEW 43.1 kSps sample rate conversion 400 kSps 51.8 kSps 256 FFT, tone select 51.8 kSps 368.3 kSps testbench control/data visualization differential MCX pair TX Chassis RX Chassis 1 × PXIe-1082 1 × PXIe-8133 1 × PXIe-7965R 1 × NI-5781 FAM differential MCX pair (quadrature component = 0) 1 × PXIe-1082 1 × PXIe-8133 2 × PXIe-7965R 1 × NI-5781 FAM Background | System Design and Implementation | Demo | Conclusion

12. 11 AMPEQ.lvdsp (first half) Background | System Design and Implementation | Demo | Conclusion (second half)

13. Results 12 Background | System Design and Implementation | Demo | Conclusion UtilizationTrans.Rec.AMP+Eq FPGA123 total slices32.6%64.0%94.2% slice reg.15.8%39.3%59.0% slice LUTs17.6%42.4%71.4% DSP48s2.0%7.3%27.3% blockRAMs7.8%18.4%29.1% Received QPSK constellation at equalizer output conventional receiverwith AMP Resource Utilization

14. Bit-Error-Rate Measurements 13 Background | System Design and Implementation | Demo | Conclusion

15. DEMO Background | System Design and Implementation | Demo | Conclusion 14

16. Conclusions Background | System Design and Implementation | Demo | Conclusion 15 Used LabVIEW DSP Designer to implement real-time PLC OFDM impulsive noise mitigation test system Achieved measured performance of up to 8 dB of impulsive noise mitigation across typical PLC SNR range Paper summarizing project submitted to 2013 IEEE Asilomar Conference on Signals, Systems and Computers: http://users.ece.utexas.edu/~bevans/papers/2013/fpgaReceiver (in progress) publishing LV project and simulations http://users.ece.utexas.edu/~bevans/papers/2013/fpgaReceiver

17. Thank you for your attention! 16 Background | System Design and Implementation | Demo | Conclusion