1. George Mason University ECE 448 FPGA and ASIC Design with VHDL FPGA Design Flow ECE 448 Lecture 7

2. 2ECE 448 – FPGA and ASIC Design with VHDL Resources & Required Reading Integrated Interfaces: Active-HDL with Synplify® Integrated Synthesis and Implementation Movie Demos Active-HDL Help

3. 3ECE 448 – FPGA and ASIC Design with VHDL Design flow (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis

4. 4ECE 448 – FPGA and ASIC Design with VHDL Design flow (2) Implementation Configuration Timing simulation On chip testing

5. 5ECE 448 – FPGA and ASIC Design with VHDL Design Process control from Active-HDL

6. 6ECE 448 – FPGA and ASIC Design with VHDL Simulation Tools Many others…

7. 7ECE 448 – FPGA and ASIC Design with VHDL

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9. George Mason University ECE 448 FPGA and ASIC Design with VHDL Synthesis

10. 10ECE 448 – FPGA and ASIC Design with VHDL Synthesis Tools … and others Synplify Pro Xilinx XST

11. 11ECE 448 – FPGA and ASIC Design with VHDL architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

12. 12ECE 448 – FPGA and ASIC Design with VHDL Features of synthesis tools Interpret RTL code Produce synthesized circuit netlist in a standard EDIF format Give preliminary performance estimates Display circuit schematic corresponding to EDIF netlist

13. 13ECE 448 – FPGA and ASIC Design with VHDL Timing report after synthesis Performance Summary ******************* Worst slack in design: -0.924 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------- exam1|clk 85.0 MHz 78.8 MHz 11.765 12.688 -0.924 inferred Inferred_clkgroup_0 System 85.0 MHz 86.4 MHz 11.765 11.572 0.193 system default_clkgroup ===========================================================

14. George Mason University ECE 448 FPGA and ASIC Design with VHDL Defining Constraints

15. 15ECE 448 – FPGA and ASIC Design with VHDL Pin Assignment LAB2 CLOCK CONTROL(0) CONTROL(2) CONTROL(1) RESET SEGMENTS(0) SEGMENTS(1) SEGMENTS(2) SEGMENTS(3) SEGMENTS(4) SEGMENTS(5) SEGMENTS(6) P10 K2 N6 K3 R7 K4 T7 M6 M11 R10 P8 E11 FPGA

16. 16ECE 448 – FPGA and ASIC Design with VHDL XSA Board – XSA-3S1000

17. 17ECE 448 – FPGA and ASIC Design with VHDL FPGA device present on the board XC3S1000-4FT256 Spartan 3 family 1000 k = 1 M equivalent logic gates speed grade -4 = standard performance 256 pins package type

18. 18ECE 448 – FPGA and ASIC Design with VHDL Arrangement of Components

19. 19ECE 448 – FPGA and ASIC Design with VHDL XSA Board Connectivity

20. 20ECE 448 – FPGA and ASIC Design with VHDL DIP Switches and Pushbuttons

21. 21ECE 448 – FPGA and ASIC Design with VHDL 100 MHz Programmable Oscillator

22. 22ECE 448 – FPGA and ASIC Design with VHDL

23. 23ECE 448 – FPGA and ASIC Design with VHDL

24. 24ECE 448 – FPGA and ASIC Design with VHDL

25. 25ECE 448 – FPGA and ASIC Design with VHDL Sample UCF File NET "clock" LOC = "P8"; NET "control " LOC = "K4"; NET "control " LOC = "K3"; NET "control " LOC = "K2"; NET "reset" LOC = "E11"; NET "segments " LOC = "R10"; NET "segments " LOC = "P10"; NET "segments " LOC = "M11"; NET "segments " LOC = "M6"; NET "segments " LOC = "N6"; NET "segments " LOC = "T7"; NET "segments " LOC = "R7";

26. 26ECE 448 – FPGA and ASIC Design with VHDL Pin Assignment LAB2 CLOCK CONTROL(0) CONTROL(2) CONTROL(1) RESET SEGMENTS(0) SEGMENTS(1) SEGMENTS(2) SEGMENTS(3) SEGMENTS(4) SEGMENTS(5) SEGMENTS(6) P10 K2 N6 K3 R7 K4 T7 M6 M11 R10 P8 E11 FPGA

27. George Mason University ECE 448 FPGA and ASIC Design with VHDL Implementation

28. 28ECE 448 – FPGA and ASIC Design with VHDL Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

29. 29ECE 448 – FPGA and ASIC Design with VHDL

30. 30ECE 448 – FPGA and ASIC Design with VHDL Translation UCF NGD EDIF NCF Native Generic Database file Constraint Editor User Constraint File Native Constraint File Electronic Design Interchange Format Circuit netlistTiming Constraints Synthesis

31. 31ECE 448 – FPGA and ASIC Design with VHDL Circuit netlist

32. 32ECE 448 – FPGA and ASIC Design with VHDL Mapping LUT2 LUT3 LUT4 LUT5 LUT1 FF1 FF2 LUT0

33. 33ECE 448 – FPGA and ASIC Design with VHDL Placing CLB SLICES FPGA

34. 34ECE 448 – FPGA and ASIC Design with VHDL Routing Programmable Connections FPGA

35. 35ECE 448 – FPGA and ASIC Design with VHDL Configuration Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

36. 36ECE 448 – FPGA and ASIC Design with VHDL Report files

37. 37ECE 448 – FPGA and ASIC Design with VHDL Map report header Release 7.1.03i Map H.41 Xilinx Mapping Report File for Design 'exam1' Design Information ------------------ Command Line : c:\Xilinx\bin\nt\map.exe -p 2S200FG256-6 -o map.ncd -pr b -k 4 -cm area -c 100 -tx off exam1.ngd exam1.pcf Target Device : xc2s200 Target Package : fg256 Target Speed : -6 Mapper Version : spartan2 -- $Revision: 1.26.6.4 $ Mapped Date : Wed Nov 02 11:15:15 2005

38. 38ECE 448 – FPGA and ASIC Design with VHDL Map report Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 144 out of 4,704 3% Number of 4 input LUTs: 173 out of 4,704 3% Logic Distribution: Number of occupied Slices: 145 out of 2,352 6% Number of Slices containing only related logic: 145 out of 145 100% Number of Slices containing unrelated logic: 0 out of 145 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 210 out of 4,704 4% Number used as logic: 173 Number used as a route-thru: 5 Number used as 16x1 RAMs: 32 Number of bonded IOBs: 74 out of 176 42% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25

39. 39ECE 448 – FPGA and ASIC Design with VHDL Place & route report Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- TS_clk = PERIOD TIMEGRP "clk" 11.765 ns | 11.765ns | 11.622ns | 13 HIGH 50% | | | -------------------------------------------------------------------------------- OFFSET = OUT 11.765 ns AFTER COMP "clk" | 11.765ns | 11.491ns | 1 -------------------------------------------------------------------------------- OFFSET = IN 11.765 ns BEFORE COMP "clk" | 11.765ns | 11.442ns | 2 --------------------------------------------------------------------------------

40. 40ECE 448 – FPGA and ASIC Design with VHDL Post layout timing report Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 42912 paths, 0 nets, and 1038 connections Design statistics: Minimum period: 11.622ns (Maximum frequency: 86.044MHz) Minimum input required time before clock: 11.442ns Minimum output required time after clock: 11.491ns

41. 41ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analysis

42. 42ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency

43. 43ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analysis Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period

44. 44ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analysis Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers DQ in clk DQ out t P logic t Critical = t P FF + t P logic + t S FF

45. 45ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits Combinational Circuits Are Characterized by Propagation Delays through logic components (gates, LUTs) through interconnects (routing delays) t p LUT t p routing LUT Total propagation delay through combinational logic

46. 46ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits (2) Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components Number of logic levels is the number of logic components (gates, LUTs) the signal propagates through Routing Delays Depend on: Length of interconnects Fanout

47. 47ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits (3) Fanout – Number of Inputs Connected to One Output Each inputs has its capacitance Fast switching of outputs with high fanout requires higher currents and strong drivers LUT

48. 48ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits (4) In Current Technologies Routing Delays Make 50-70% of the Total Propagation Delays

49. 49ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Sequential Circuits (1) Timing Features of Flip-flops Setup time t S – minimum time the input has to be stable before the rising edge of the clock Hold time t H – minimum time the input has to be stable after the rising edge of the clock Propagation delay t P – time to propagate input to output after the rising edge of the clock

50. 50ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Sequential Circuits (2) DQ clk D Q tStS tHtH tPtP Input D must remain stable during this interval Input D can freely change during this interval

51. 51ECE 448 – FPGA and ASIC Design with VHDL Timing simulation after implementation

52. 52ECE 448 – FPGA and ASIC Design with VHDL Timing vs. functional simulation Simulation before synthesis is used to verify circuit functionality and may differ from the one after synthesis and implementation Implementation tool generates SDF (Standard Delay Format) as a standard delay file and the netlist for synthesized VHDL code with delays. Generated netlist contains many component instantiation statements with library references

53. 53ECE 448 – FPGA and ASIC Design with VHDL SDF file ( DELAYFILE ( CELL( CELLTYPE “XOR”) ( INSTANCE U34.Z_VTX) ( DELAY( INCREMENT ( DEVICE 01 0.385090:0.385090:0.385090 (0.385090:0.385090:0.385090)(0.235177: 0.235177: 0.235177) ) ) ) ) A part of the SDF file is shown below. It indicates XOR gate delays (low to high, high to low) of minimum, typical and worst case timing

54. 54ECE 448 – FPGA and ASIC Design with VHDL Netlist from the synthesis tool library IEEE; library TC200G; use IEEE.std_logic_1164.all; use TC200G.components.all; entity CONSYN is port( RSTn, CLK, D0, D1, D2, D3, D4, D5, D6, D7 : in std_logic; FF_OUT, COMB_OUT, FF_COMB_OUT : out std_logic); end CONSYN; architecture structural of CONSYN is signal XOR8, FF, n70, n71, n72, n73, n74, n75, n76, n67, n68, n69 : std_logic; begin FF_OUT <= FF; COMB_OUT <= XOR8; FF_reg : FD2 port map( Q => FF, QN => n75, D => XOR8, CP => CLK, CD => RSTn) ; U30 : MUX21L port map( Z => n71, A => n67, B => n68, S => n69); U31 : EN port map( Z => n67, A => D1, B => D0); U32 : IV port map( Z => n68, A => n67); U33 : EOP port map( Z => n69, A => D6, B => D7); U34 : EO3 port map( Z => n70, A => D3, B => D2, C => D4); U35 : EO port map( Z => n72, A => D5, B => n70); U36 : EOP port map( Z => XOR8, A => n72, B => n71); U37 : FA1A port map( S => n73, CO => n76, CI => D3, A => D2, B => FF); U38 : EO3 port map( Z => n74, A => n68, B => n73, C => D4); U39 : EOP port map( Z => FF_COMB_OUT, A => D5, B => n74); end structural;