1. WISP

2. Content Hardware Architecture Microcontroller Code MSP430F2132
Operating Modes & Interrupts
Code
High-level States
Communication Layer

3. Hardware Architecture
Voltage Supervisor + Voltage Regulator
Antenna gets RF signal
External Voltage Supervisor tells MCU when to wake up
MCU processes bits and performs Gen 2 protocol
Polls sensors to gather data
Maximize power transfer to Power Harvester
RF signal rectified into DC voltage
Interprets signal into bits + converts bit voltage level to be Vreg
Transistor that changes antenna impedance for ‘backscatter’

4. Microcontroller MSP430F2132 Architecture General Information Frequency
16 MHz
Flash/ROM
8 KB
RAM
512 Bytes
Information Memory
256 Bytes
Clock System
ACLK
32.7 MHz watch crystal
MCLK
Used by CPU
SMCLK
What is consumed by RFID code:
Timer
0.25 of 8K flash
RAM – volatile variables. Small chunk
Port 1 for Comm
Port 2 for SV INT
Port 3 for debugging (no interrupt capability)
Cannot share P1 interrupts or timer capture/compare interrupts (timing sensitive for comm)
16 MHz = 3.6V
Used by Peripheral Modules
Consumed by RFID
RAM – variables. Small chunk used
Port 1 Interrupt used for Communication.
Port 2 Interrupt used for Voltage Supervisor – can be shared
Port 3 for debugging (no interrupt capability)
2 Timer counter interrupts (one used for communication)
Used 4 pins total out of 24 GPIO

5. Available Interrupts vs. Sleep State Available Clocks vs. Sleep State
Microcontroller
Operating Modes
Interrupts
Types
Non-Maskable: NMI pin, Oscillator fault, flash access violation
Maskable: Peripherals and WDT in Interval Mode
> 1 peripheral interrupt pending simultaneously
In 2132:
Comparator
Brownout Protection
RAM
Flash
…higher priority > WDT
Available Interrupts vs. Sleep State
Active Mode
All Interrupts
LPM0, LPM1, LPM2, LPM3
ADC, WDT, Timer, External
LPM4
External
What is Vcc?
What are System Resets?
Interrupt Processing
NORMAL
GIE on by developer
NESTED
Available Clocks vs. Sleep State
GIE on by developer
Interrupt Service Routine
Active Mode
All Clocks. CPU active (~200uA/MHz)
Interrupt Service Routine
Interrupt Service Routine
GIE turned off by Hardware
Interrupt serviced
GIE turned on by Hardware
LPM0/1
All Clocks. CPU off (~30uA/MHz)
GIE turned off by Hardware
GIE turned on by developer
LPM2/3
DCO off. LFOSC on. CPU off ~10kHz)
LPM4
All disabled (0.1uA)
All pre-Interrupt settings in place
New Interrupt serviced w/o priority

6. Code
High-Level States

7. Code Communication Layer Receive EPC State Machine Transmit
Port 1 Interrupt & GIE Enabled
Setup to Receive LPM4 No
Timer value wrt bit length & encoding
Enough # bits
Port 1 Interrupt
Yes No
Timer Interrupt Enabled
Correct Command
Yes
Process packet
Port 1.1
delimiterNotFound = 1
Flip Port 1 transmit pin at timer interrupt
Timer Reset at every positive edge
Each bit pushed into register
Timer not reset (i.e. no bit)
WISP breaks out of communication layer