1. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 1 FPPA Analog Output Buffer Modifications Outline Status Slew Rate Bias lines disturbance Modifications New Output Buffer performances

2. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 2 Status : Remember For each CFA

3. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 3 Status (1) Problems discovered in the FPPA2001 output buffer. Extrinsic problem. Faster slew-rate from FPU impose to increase slew-rate and improve stability. Intrinsic problems. Bad Slew rate in the PNP emitter follower of the input stage (PPbuffer cell). –Rise time variation versus amplitude. Voltage variation on the bias lines nbias and pbias. –Oscillation during settling time.

4. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 4 Status (2) Faster signal from FPU (slew-rate enhanced)

5. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 5 Status (3) Slew-rate from FPU = 1000V/us

6. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 6 Status (4) Bad response of Output Buffer Consequently, bad settling time and bad resolution ( + a little oscillation)

7. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 7 Slew-Rate (1) (3) (2) NPN emitter follower output PNP emitter follower output Input (3) (2) (1) In + In - Observed slew rate Slowly slew-rate (the first branch has not enough current to drive the second branch)

8. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 8 Bias lines disturbance (1) (3) (2) (1) (2) (3) (biasfpua) From bias generator (3) (2) Oscillation during settling time Come from local bias generator PPbias PPbuffer

9. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 9 Modifications To improve slew-rate and stability, we must modify local bias and buffer architecture Add 2 emitter followers in parallel for improving the slew rate This lower the impedance of the bias lines mbias and pbias Add 5K resistor Add a booster Add extra vdda connection from bias generator

10. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 10 Layout Modifications Old PPbuffer layoutNew PPbuffer layout More vias between M1 and M2 New cells New PPbias layout New cells Differential connections from Bias generator (between vdd and signal)

11. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 11 New FPPA Analog Buffer Analysis

12. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 12 New Output Buffer performances (1) Accurate response with stable signal over 12 bits

13. 14 June 2002 P.Pangaud FPPA2001 2nd Design Review 13 New Output Buffer performances (2) AC response : - Bandwidth (-3dB) = 245 Mhz - Output noise (rms) = 147 uV Transient response : - Power consumption : 140 mW - Time rise : 1.6 ns - Time fall : 2 ns - Delay : 1.8 ns - Settling Time (0.1%) = 5.7 ns FPPA2000 FPPA2001 FPPA’s Global simulations (R + C parasitics) versus