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1 68HC11 Timer Chapter 10. 2 68HC11 Timer Subsystem Several timing functions: Basic timing Basic timing Real time interrupts Real time interrupts Output.

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Presentation on theme: "1 68HC11 Timer Chapter 10. 2 68HC11 Timer Subsystem Several timing functions: Basic timing Basic timing Real time interrupts Real time interrupts Output."— Presentation transcript:

1 1 68HC11 Timer Chapter 10

2 2 68HC11 Timer Subsystem Several timing functions: Basic timing Basic timing Real time interrupts Real time interrupts Output compare Output compare Input capture Input capture Computer Operating Properly Computer Operating Properly Pulse Accumulator Pulse Accumulator Pulse Width Modulation Pulse Width Modulation Common Features Based on a central timer Based on a central timer Overflow Flags Overflow Flags Interrupt Enables Interrupt Enables

3 3 Timer System Block Diagram

4 4 Basic Timer

5 5 Basic Timer– TCNT $100E 16-bit free running counter (timer) Cannot be set or stopped. Cannot be set or stopped. Fclk = system clock Can be prescaled by 1,4,8, or 16 Read only at memory address ($100E) Overflow flag is bit 7 in TFLG2 ($1025) Overflow flag is bit 7 in TFLG2 ($1025) Can use overflow to extend counter’s range Timer Overflow Interrupt Enable Timer Overflow Interrupt Enable Bit 7 in TMSK ($1024)

6 6 TCNT - $100E:$100F Timer Counter Register 76543210 Bits CNT15 READ ONLY Register CNT13CNT12CNT11CNT10CNT9CNT8 CNT14 76543210 CNT7 CNT5CNT4CNT3CNT2CNT1CNT0 CNT6 $100E $100F

7 7 Prescaler 76543210 Bits PR2 PR1PAII00PAOVIRTHTOI Timer Interrupt Mask Register 2: $1024 -- TFLG2 PR1,PR0 = Timer prescale select - Timer Clock = System Clock / Prescale Factor Pr1 Pr0 Prescale Factor 0 0 1 0 1 2 1 0 4 1 1 16

8 8 Timer Overflow Flag 76543210 Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) TOF = Timer overflow flag - 0 = No overflow 1 = Overflow TOF is reset to 0 by writing ‘1’ to TOF

9 9 Timer Overflow Interrupts 76543210 Bits PR2 PR1PAII00PAOVIRTHTOI Timer Interrupt Mask Register 2: $1024 (TMSK2) TOI = Timer overflow interrupt enable 0 = disable interrupt 1 = enable interrupt

10 10 Basic Timer Example Problem: Write an ISR to read the input from PortC and write it to PortB approximately every 1,000,000 clock cycles. Assume timer prescale = 1

11 11 Basic Timer Example Main Program Configure Timer Overflow Interrupt TMSK2(7)  ‘1’ TMSK2(7)  ‘1’ Enable Interrupts (CLI) Repeat Until Forever Set Timer Overflow Interrupt Vector ORG TOI_VECTOR ($FFDE:FFDF) ORG TOI_VECTOR ($FFDE:FFDF) FDB TO_ISR FDB TO_ISR

12 12 Basic Timer Example TO_ISR Disable Interrupts SEI SEI Turn-off Interrupt Request TOF  ‘1’ TOF  ‘1’ CNT = CNT + 1 IF CNT = MAX_CNT then CNT = 0 CNT = 0 A  PORTC A  PORTC PORTB  A PORTB  A END IF Return from Interrupt

13 13 Basic Timer Example MAX_CNT Calculation Need to wait 1,000,000 or $F4240 clock cycles. Interrupt is generated every 65536 or $10000 clock cycles Max_CNT = INT(1,000,000 / 65556) = 15.258 ~ 15 = $F Note: INT($F4240/$10000) = $F Note: INT($F4240/$10000) = $F Set MAX_CNT EQU $F

14 14 Real Time Interrupt

15 15 Real Time Interrupt Similar to Timer Overflow Interrupt except We have: RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) System Clock is first divided by $1000 then divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026) System Clock is first divided by $1000 then divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026)

16 16 Real Time Interrupt Enable 76543210 Bits PR2 PR1PAII00PAOVIRTIITOI Timer Interrupt Mask Register 2: $1024 (TMSK2) RTII = Real Time Interrupt Enable 0 = disable interrupt 1 = enable interrupt

17 17 Real Time Interrupt Flag 76543210 Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) RTIF = Real Time Interrupt flag - 1 = RTI has occurred RTIF is reset to 0 by writing ‘1’ to RTIF

18 18 Real Time Interrupt Prescale 76543210 Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 RTR1, RTR0= Real Time Interrupt Prescale RTR1 RTR0 Nominal RTI rate (2MHz E-Clock) 0 0 4.096ms 0 1 8.192ms 1 0 16.384ms 1 1 32.768ms Port A Control Register: $1026 (PACTL)

19 19 TPS Quiz

20 20 Computer Operating Properly COP

21 21 Computer Operating Properly COP Also known as a “watchdog” timer When enabled, your program must set the COP timer and reset the COP timer prior to the COP’s “time-out” delay. This time-out delay is programmable. When enabled, your program must set the COP timer and reset the COP timer prior to the COP’s “time-out” delay. This time-out delay is programmable. If the program does not set or reset the COP timer before the “time-out”, a COP failure interrupt is generated and the ISR assigned to the interrupt is executed. If the program does not set or reset the COP timer before the “time-out”, a COP failure interrupt is generated and the ISR assigned to the interrupt is executed.

22 22 Computer Operating Properly COP Usage Design your program to set and reset the COP before time-out. Design your program to set and reset the COP before time-out. If your program enters an infinite loop, the COP timer will “time-out” automatically causing a COP failure interrupt. If your program enters an infinite loop, the COP timer will “time-out” automatically causing a COP failure interrupt. Use the COP failure ISR to place your system into a “safe” mode or restart mode. Use the COP failure ISR to place your system into a “safe” mode or restart mode.

23 23 Output Compare

24 24 Timer Output Compare Using the timer overflow flag or interrupt will generate a count every 65536 clock cycles. Given a 2MHz clock, this gives a sample resolution of 32.8ms The timer output compare feature allows for more precise timing.

25 25 Timer Output Compare There are five output compare registers Each with a separate Compare Counter Compare Counter Interrupt Mask Interrupt Mask Overflow Flag Overflow Flag

26 26 TOC1 – TOC5 Timer Output Compare Registers 76543210 Bits OCn15 TOC1 - $1016:$1017 TOC2 - $1018:$1019 TOC3 - $101A:$101B OCn13OCn12OCn11OCn10OCn9OCn8 OCn14 76543210 OCn7 OCn5OCn4OCn3OCn2OCn1OCn0 OCn6 TOC4 - $101C:$101D TOC5 - $101E:$101F

27 27 Output Compare Flags 76543210 Bits IC3F IC2FOC4FIC1FOC5FOC3FOC2FOC1F Main Timer Interrupt Flag Register 1: $1023 (TFGL1 ) OC1F-OC5F = Output Compare Flags 1 = when output compare register equals TCNT 0 = reset by writing ‘1’ to bit position

28 28 Output Compare Interrupts 76543210 Bits IC3I IC2IOC4IIC1IOC5IOC3IOC2IOC1I Main Timer Interrupt Mask Register 1: $1022 (TMSK1) OC1I-OC5I = Output Compare interrupt enable 0 = disable interrupt 1 = enable interrupt

29 29 Output Compare Example Problem: Write an ISR to read the input from PortC and write it to PortB approximately every 10,000 clock cycles. Assume timer prescale = 1 Note: 10,000 cycles is less than one timer overflow!!

30 30 Output Compare Example Main Program A  TCNT ; Load current count TOC1  A + 10000 ; Add 10000 to current count Configure Output Compare 1 Interrupt Configure Output Compare 1 Interrupt TMSK1(7)  ‘1’ TMSK1(7)  ‘1’ Enable Interrupts (CLI) Repeat Until Forever Set Output Compare 1 Interrupt Vector ORG OC1_VECTOR ($FFE8:FFE9) ORG OC1_VECTOR ($FFE8:FFE9) FDB OC1_ISR FDB OC1_ISR

31 31 Output Compare Example OC1_ISR Disable Interrupts SEI SEI Turn-off Interrupt Request OC1F  ‘1’ OC1F  ‘1’ A  PORTC PORTB  A A  TCNT ; Load current count TOC1  A+10000 ; update TOC1 for next interrupt interrupt Return from Interrupt

32 32 Input Capture

33 33 Timer Input Capture 16-bit TCIx Latch Det Ckt TCNT clk Ext Signal When the Ext Signal is detected on pin PAx, the current value of the free running counte TCNT is latched into the timer input capture latch. This value can be read and saved to determine the time between events. PAx

34 34 Timer Input Capture The timer input capture feature can be used to time external events Three input capture registers TIC1 : $1010:$1011 TIC1 : $1010:$1011 TIC2 : $1012:$1013 TIC2 : $1012:$1013 TIC3: $1014:$1015 TIC3: $1014:$1015 Maximum time between events must be less than 65536 cycles

35 35 TIC1 – TIC3 Timer Input Capture Registers 76543210 Bits ICn15 TIC1 - $1010:$1011 TIC2 - $1012:$1013 TIC3 - $1014:$1015 ICn13ICn12ICn11ICn10ICn9ICn8 ICn14 76543210 ICn7 ICn5ICn4ICn3ICn2ICn1ICn0 ICn6

36 36 Input Compare Interrupts 76543210 Bits IC3I IC2IOC4IIC1IOC5IOC3IOC2IOC1I Main Timer Interrupt Mask Register 1: $1022 (TMSK1) IC1I-IC3I = Input Compare interrupt enable 0 = disable interrupt 1 = enable interrupt

37 37 Interrupt Capture Flags 76543210 Bits IC3F IC2FOC4FIC1FOC5FOC3FOC2FOC1F Main Timer Interrupt Flag Register 1: $1023 (TFGL1 ) IC1F-IC3F = Interrupt Capture Flags 1 = when selcted edge is detected 0 = reset by writing ‘1’ to bit position

38 38 Timer Control Register 2 TCTL2 - $1021 76543210 Bits EDG1BEDG1AEDG2BEDG2AEDG3BEDG3A00 EDGnB EDGnA Configuration 0 0 Disabled 0 1 Rising Edge 1 0 Falling Edge 1 1 Either Edge

39 39 Pulse Accumulator

40 40 Pulse Accumulator The pulse accumulator can be used as an event counter. That is, it can count the number of external events. Note: difference to Timer Input Capture which counts the time between external events. Configuration: PACTL ($1026) is used to configure PA PACTL ($1026) is used to configure PA PACNT ($1027) is the PA Count Register PACNT ($1027) is the PA Count Register Two Modes: Event Counting: PA7 is External Clock Event Counting: PA7 is External Clock Gated Time Accumulation: PA7 is enable to system clock divided by 64 Gated Time Accumulation: PA7 is enable to system clock divided by 64

41 41 PACTL: $1026 Port A Control Register 76543210 Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 PAEN6 = Pulse Accumulator System Enable 0 = Disable (Default) Port A is set for I/O function 1 = Enable Port A is set for Pulse Accumulator function PAMOD= Pulse accumulator mode 0 = Event counter (Default) 1 = Gated time accumulation

42 42 PACTL: $1026 Port A Control Register 76543210 Bits RTR0RTR1 PEDGEPAMODPAEN6DDRA7 00 PEDGE= Pulse Accumulator Edge Select 0 = Falling Edge (in event mode) – Active High (in gated mode) 1 = Rising Edge (in event mode) – Active Low (in gated mode)

43 43 Pulse Accumulator Flag 76543210 Bits 0 0PAIF00PAOVFRTIFTOF Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2) PAOVF = Pulse Accumulator Overflow Flag 1 = Overflow has occurred PAOVF is reset to 0 by writing ‘1’ to PAOVF PAIF = Pulse Accumulator Input Edge Flag 1 = Input edge has been detected PAIF is reset to 0 by writing ‘1’ to PAIF

44 44 Pulse Accumulator Interrupts 76543210 Bits PR2 PR1PAII00PAOVIRTIITOI Timer Interrupt Mask Register 2: $1024 (TMSK2) PAOVI = Pulse Accumulator overflow interrupt enable 0 = disable interrupt 1 = enable interrupt PAII = Pulse Accumulator input edge interrupt enable 0 = disable interrupt 1 = enable interrupt

45 45 Pulse Width Modulation

46 46 Pulse Width Modulation Some versions of 68HC11 have a pulse width modulation (PWM) module which can be used to generate periodic output waveforms with a specific period and duty cycle (i.e. the percentage of time the signal is high compare to when it is low).

47 47 Timer Summary Timer subsystem – most complex in 68HC11 Based on free running timer Timings available: Basic timing Basic timing Real time interrupts Real time interrupts Output compare Output compare Input capture Input capture Computer Operating Properly Computer Operating Properly Pulse Accumulator Pulse Accumulator Pulse Width Modulation Pulse Width Modulation Overflow flags and/or Interrupts are available

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