1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 Robert Mars

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Design Slide 2

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Adder Parallel Prefix Adder: Han-Carlson Sklansky Nehru Slide 3 Quelle: Nehru and Shanmugam: Design of 64 Bit Parallel Prefix Adder using Transmission Gate (2012)

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Supply Voltage Lowest power at 1,0V Vdd Best metric at 1,0V Vdd Used CORE65LPLVT library Slide 4

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Frequency Power increases with frequency Best metric at 1700 MHz Slide 5

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Compile options Synopsys Design Compiler Reference Methodology Training: https://solvnet.synopsys.com/retrieve/customer/script/attached_files/021023/DC-RM_Training_F-2011.09-SP4.pdf Slide 6

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Compile options compile_ultra  best quality of results and performance -retime  adaptive retiming to improve delay -exact_map  mapping of sequential cells exactly as in VHDL code -gate_clock  perform clock gating -scan/-timing_high_effort/-congestion  no improvement -spg  only available in topographical mode optimize_registers  minimizes flip-flop count while maintaining clock period balance_buffer  creates balanced buffer tree Slide 7

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Mandatory values for ASIC Backanno tation Frequency [MHz] 1700 Area2720 Power [µW] 5615 # Pipeline Stages2 Metric [MHz²/µW] 514 Slide 8

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention Slide 9