1. Spring 2006 1 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Advanced Computer Architecture Lecture 9 DMA controller design

2. Spring 2006 2 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Direct memory access Objective: avoid the disadvantages of programmed I/O (eliminate the busy loop) Technique –CPU writes to special controller (word count and memory address) –CPU tells controller to start data transfers –CPU continues with other computing –CPU responds to interrupt from controller: ISR

3. Spring 2006 3 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Role of DMA controller Accept initialization data from CPU Access I/O device and drive bus (master) –Input: read I/O device and write data to memory –Output: read memory data and write to I/O device Interrupt CPU when transfer complete

4. Spring 2006 4 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA hardware view n words adr X adr X+(n-1) Memory I/O device buffer System busadr 0 adr n-1

5. Spring 2006 5 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller architecture Counts up from zero Counts down to zero Preset counter Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr 5 key blocks

6. Spring 2006 6 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA initialization instructions? 1.Write start address 2.Write word count (or end address) 3.Write “go” command Each write is to a specific DMA controller port address

7. Spring 2006 7 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller initialization 1 Start address Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

8. Spring 2006 8 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller initialization 2 Word count Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

9. Spring 2006 9 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller initialization 3 Start Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

10. Spring 2006 10 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller driving bus Must enable all tri-state drivers: D, A, and C buses D bus sources the data, memory agent sinks the data A bus contains the memory address decoded by memory agent C bus contains the memory write code

11. Spring 2006 11 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller driving bus Memory write Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr Memory adr Memory data

12. Spring 2006 12 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Hard drive DMA Assumptions –Operation: Input, or read disk, or read file –HD buffer: represent with a ROM Initialization commands –Port 1: start address –Port 2: word count –Port 4: start Design contains 5 sections Project 5

13. Spring 2006 13 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Buffer address section Objective: create an address for the HD buffer (ROM) Role: zero counter, count up

14. Spring 2006 14 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Buffer address block?

15. Spring 2006 15 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Data buffer section Objective: provide data for bus transfers Role: drive the data bus when enabled and addressed

16. Spring 2006 16 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Data buffer block?

17. Spring 2006 17 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Word count section Objective: keep track of how many data words have been transferred Role: preset to some number, then count down to zero, indicate zero condition

18. Spring 2006 18 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Word count block?

19. Spring 2006 19 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Memory address section Objective: provide address for bus transfer Role: accept start address, then count up, drive the address bus

20. Spring 2006 20 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Memory address block?

21. Spring 2006 21 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Updated block diagram Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr Port1 Port2 BAclr BAinc WCdec MAinc Zero Ben Count

22. Spring 2006 22 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section Objective: decode the Port instructions, request bus, transfer data across the bus, coordinate the sequence of the other blocks, interrupt CPU when done Role –Contains three subsections: decoder, counters, bus I/F –Bus I/F a FSM similar to CPU model

23. Spring 2006 23 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 1? Decode

24. Spring 2006 24 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 2? Counters

25. Spring 2006 25 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 3? Bus interface

26. Spring 2006 26 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering

27. Spring 2006 27 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Buffer address block? Buffer Address BAclr BAinc BAdr

28. Spring 2006 28 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Data buffer block? Data Buffer (ROM) Data Ben BAdr Assume ROM outputs are tri-state

29. Spring 2006 29 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Word count block? Word Count Data WCload WCdec Zero

30. Spring 2006 30 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Memory address block? Memory Address A Assume MA outputs are tri-state D MAload MAinc Ben

31. Spring 2006 31 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 1? Decode Logic C A Port1 (MAload) Port2 (WCload) Port4 (Start) Decode

32. Spring 2006 32 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 2? Enables Start BAclr BAinc WCdec MAinc Zero Counters One signal?

33. Spring 2006 33 EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 3? Bus I/F Bgnt Breq Int Ben Ack Inta C Must drive C bus with memory write instruction Bus interface