1. III-V HBT device physics: what to include in future compact models rodwell@ece.ucsb.edu 805-893-3244, 805-893-2362 fax Mark Rodwell University of California, Santa Barbara Workshop on Compact Modeling for RF-Microwave Applications, Oct.. 3, 2007, Boston, Mass.

2. Fast InP Transistors: What Are They For ? microwave ADCs and DACs more resolution & more bandwidth microwave op-amps high IP3 at low DC power at 2-10 GHz 340 GHz or 650 GHz imaging systems Power amplifiers for V-band & W-band single-chip 300-600 GHz spectrometers (gas detection)

3. Current IC Projects → Modeling Challenges 340 GHz, 70 mW amplifiers (DARPA SWIFT) device and IC layout parasitics breakdown & safe operating area, thermal stability  f and C cb over full signal swing 200 GHz digital logic C cb vs (I c, V ce ) ---precise modelling of Kirk effect for low C/I IC interconnect modelling mm-wave op-amps→ low IM3 @ 2 GHz Ccb vs Ic and Vce----residual distortion gm vs Ic --- modeling of gain, and of gm nolinearities compact, precise modelling of interconnect parasitics---phase margin ! Z. Griffith M. Urteaga (Teledyne) Z. Griffith M. Jones (UCSB), J. Hacker (Teledyne)

4. Technology Status & Roadmap

5. 512 nm InP DHBT: Low-Volume Production Production DDS IC: 4500 HBTsmm-wave op-amps 500 nm mesa HBT 150 GHz M/S latches175 GHz amplifiers Laboratory Technology Teledyne / BAETeledyne / UCSB UCSBUCSB / Teledyne / GCS 500 nm sidewall HBT f  = 405 GHz f max = 392 GHz V br, ceo = 4 V Teledyne 20 GHz clockhigh OIP3 @ 2 GHz with low power dissipation ( Teledyne )

6. 256 nm InP DHBT: Research→ Development 150 nm thick collector 70 nm thick collector 60 nm thick collector 340 GHz, 70 mW amplifier design 200 GHz master-slave latch design

7. THz Bipolar Transistors

8. 1 st - Order Design of Bipolar Transistors SiO 2 P base N+ subcollector N- spreadinglinkcontact

9. 1 st - Order Design of a 1 THz Bipolar Transistor InPSiGe emitter64 18?nm width 2 0.6*A cont /A junct  m 2 access  base60 ____nm contact width, 2.5 0.7*A total /A cb overlap  m 2 contact  collector53 15 nm thick 36 126?mA/  m 2 current density 2.75 ______V, breakdown f  10001000 GHz f max 20002000 GHz PAs10001000 GHz digital480 480GHz (2:1 static divider metric) SiO 2 P base N+ subcollector N-

10. HBT Design

11. Monte Carlo ? We Design HBTs By Pencil & Paper (+ EXCEL ) III-V HBTs remain well-modeled by drift-diffusion equation Hand analysis predicts quite well device cutoff frequencies, and logic speed. Underlying this, we assume 3.5E7 cm/s carrier velocity. Effective collector velocity does not seem to increase with futher scaling. BUT models with more precise physics are needed to model: variation of g m & I c with V be variation of  f and C cb with I c & V ce breakdown and safe operating area thermal instability

12. Particular attention: collector current & voltage → collector velocity → transit time, C cb, Kirk threshold second-order transport effects in base-emitter junction What Are The Challenges In Modeling ? First-order design works quite well... But, second-order transport physics introduces small corrections Of greatest importance in: IM3 prediction in amplifiers Simulation of mm-wave power amplifiers

13. HBT Physics & HBT Modelling

14. A comment on terminology D. Root

15. Base-Emitter Junction

16. Base-Emitter Junction: HBT Ic-Vbe Characterisitics 128 & 64 nm scaling generation: very high J e minority carrier concentration near, beyond N c DEGENERATE→ Fermi-Dirac, not Boltzmann roughly modeled as series resistance better modeled as V be ~ (kT/q)ln( I / I s )+k 1 I 2/3 T e =0 nm T e =100 nm 10 nm steps Voltage drops in e/b depletion region --device designers need to minimize this --to the extent that they cannot, must model well --presently modeled by R series and nkT/qI --make better model: fit to physics ?

17. Base-Emitter Junction: HBT I c -V be Characterisitics With either graded or abrupt junctions, simple exponential characteristics are expected→ 1/g m = nkT/qI c +R ex The "dip" has several implications: -we don't understand HBT operation -we cannot extract R ex from data -so, we can't seperately distinguish R ex C cb from  b +  c -compact models fail... right in the high-speed bias region -confuses analysis of "current-induced velocity modulation" abrupt EB junction 0.5 x3 um 2 Graded BE Junction 0.5 x3 um 2 Abrupt BE Junction 0.6x4 um 2 Abrupt BE Junction E. Lind M. Urteaga

18. Base-Emitter Junction: Depletion Capacitance BE depletion capacitance --needs to be modeled *exactly* in on-state (IM3 analysis) --needs to to modeled *acceptably* over logic swing (ECL & CML) The above (old ?) SPICE formalism seems ill-suited to fitting Cje vs bias for HBTs

19. Base-Collector Junction: Primary Effects

20. Collector-Base Capacitance dipoles

21. Collector-Base Capacitance

22. Kirk Effect, i.e. Space-Charge-Limited Current 0 mA/  m 2 10 mA/  m 2 Kirk ? Not ? Must model boundary of Kirk threshold in (Ic,Vce) plane. Need good RF model in space-charge-limit

23. Base-Collector Junction: Secondary Effects

24. Voltage Modulation of Collector Transit Time T. Ishibashi With increased V cb, electrons travel less distance before  -L scattering Model must incorporate some variation of collector charge storage with voltage H. Nakajima Japanese J. Appl. Phys., Vol. 36, Feb. 1997, pp. 667-668

25. Current Modulation of Collector Transit Time J=0 J= 8 mA/um 2 T. Ishibashi E. Lind

26. Transit time Modulation Causes C cb Modulation Camnitz and Moll, Betser & Ritter, D. Root

27. Transit time Modulation → Negative Resistance → Infinite Gain High extrapolated fmax in InGaAs- collector SHBTs has been reported by several groups (UCSB, Pohang,...), but relevance to mm-wave amplifiers is limited. M. Urteaga

28. Collector-base Transport Modeling: Summary Can these plots be modeled compactly, yet modeled well ?

29. Interconnects

30. fewer breaks in ground plane than CPW III-V MIMIC Interconnects -- Thin-Film Microstrip narrow line spacing → IC density... but ground breaks at device placements still have problem with package grounding thin dielectrics → narrow lines → high line losses → low current capability → no high-Z o lines H W...need to flip-chip bond no substrate radiation, no substrate losses InP mm-wave PA (Rockwell)

31. No breaks in ground plane III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip narrow line spacing → IC density... no ground breaks at device placements still have problem with package grounding thin dielectrics → narrow lines → high line losses → low current capability → no high-Z o lines...need to flip-chip bond Some substrate radiation / substrate losses InP 150 GHz master-slave latch InP 8 GHz clock rate delta-sigma ADC

32. IC design examples

33. Good Kirk-Effect Models Are Essential for ECL/CML ECL Transistors’ Load Lines

34. mm-wave Power Amplifiers

35. input power, dBm output power, dBm linear response 2-tone intermodulation increasing feedback mm-wave Op-Amps for Linear Microwave Amplification Reduce distortion with strong negative feedback R. Eden 2nd-generation ICs are working to design high IP3, ~40 GHz loop bandwidths 3rd-generation ICs are near completion simulated IP3 exceeds 53 dBm...we shall see Accurate modeling of Ccb vs bias is mission-critical UCSD (Tomas O’Sullivan, Peter Asbeck) have been critical to effort UCSB / Teledyne FLARE: Griffith & Urteaga

36. Current IC Projects → Modeling Challenges 340 GHz, 70 mW amplifiers (DARPA SWIFT) device and IC layout parasitics breakdown & safe operating area, thermal stability  f and C cb over full signal swing 200 GHz digital logic C cb vs (I c, V ce ) ---precise modelling of Kirk effect for low C/I IC interconnect modelling mm-wave op-amps→ low IM3 @ 2 GHz Ccb vs Ic and Vce----residual distortion gm vs Ic --- modeling of gain, and of gm nolinearities compact, precise modelling of interconnect parasitics---phase margin ! Z. Griffith M. Urteaga (Teledyne) Z. Griffith M. Jones (UCSB), J. Hacker (Teledyne)

37. (end)

38. Backup, Sorting, etc

39. First-Order HBT Design