1. Submicron InP Bipolar Transistors: Scaling Laws, Technology Roadmaps, Advanced Fabrication Processes Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax 2002 SSDM Conference, September, Nagoya

2. Applications of InP HBTs Optical Fiber Transceivers 40 Gb: InP and SiGe HBT both feasible ICs now available; market has vanished 80 & 160 Gb may come in time within feasibility for scaled InP HBT world may not need capacity for some time WDM might be better use of fiber bandwidth mmWave Transmission 60-80 GHz, 120-160 GHz, 220-300 GHz Low atmospheric attenuation (weather permitting). High antenna gains (short wavelengths). 10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACs high resolution at very high bandwidths sought

3. How Do We Improve the Bandwidth of Bipolar Transistors ? Thinner base, thinner collector  higher f , but higher R bb C cb, R ex C cb … what parameters are really important in HBTs ? how do we improve HBT performance ?

4. How do we improve gate delay ?

5. Scaling Laws for fast HBTs

6. Challenges with Scaling: Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowed Solution: decouple base & collector dimensions transferred-substrate, undercut-mesa, or buried SiO 2 in junction (SiGe) Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements Current Density: self-heating, current-induced dopant migration, dark-line defect formation Loss of breakdown avalanche V br never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power Yield ! submicron HBT processes have progressively decreasing yield

7. Technology Roadmaps for 40 / 80 / 160 Gb/s

8. Low C cb InP HBT structures undercut-collector transferred-substrate Allows deep submicron collector scaling Problems with heating at high J Low yield at deep submicron scaling Popular approach Uncertain yield at submicron geometries Conservative approach Still not viable for > 3000 transistors per IC Need improved device structures for high yield at 0.1  m scaling Narrow-mesa with ~1E20 carbon-doped base

9. I c = 5 mA, V ce = 1.1 V Unbounded Power Gain in Submicron InAlAs/InGaAs HBTs Unbounded 45-170 GHz Unilateral power gain Power gain is high, but f max can’t be determined Miguel Urteaga Int. Symp. Compound Semiconductors, Tokyo, Oct. 2001 Int. Journal High Speed Electronics and Systems, to be published 0.3 x 18  m 2 Emitter 0.7 x 18.6  m 2 Collector reduced Capacitance modulation & negative resistance observed: Gunn-like or IMPATT effects ?

10. Collector velocity modulation: C cb cancellation and negative resistance Miguel Urteaga If C cb cancellation is observed, there must also be an associated negative resistance

11. 2 nd Hypothesis: weak IMPATT effects in the collector Miguel Urteaga IMPATT effect also produces both capacitance cancellation and negative resistance

12. Deep Submicron Bipolar Transistors for 140-220 GHz Amplification Miguel Urteaga 1-transistor amplifier: 6.3dB @ 175 GHz 3-transistor amplifier: 8 dB @ 195 GHz raw 0.3  m transistor: 6-11 dB power gain @ 200 GHz UCSB

13. Wideband Mesa InP/InGaAs/InP DHBTs Mattias Dahlstrom (UCSB) Amy Liu (IQE) 2000 Å InP collector 300 Å InGaAs base 8E19 to 5E19 graded C base doping InAlAs/InGaAs base-collector grade. 500 Ohm/square base sheet resistance Pd/Ti/Pd/Au base Ohmic contacts < 10 -7 Ohm-cm 2 base contact resistance 7.5 V Breakdown 282 GHz f , > 450 GHz f max, operation to 500 kA/cm 2 at 1.7 volts R bb is low, C cb needs further reduction UCSB / IQE 1  m base contacts, 0.5  m emitter junction 0.7  m emitter contact V ce =1.7 V J=3.7E5 A/cm 2 282 GHz f  >450 GHz f max, 480 GHz

14. 87 GHz HBT master-slave latch InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation PK Sundararajan, Zach Griffith UCSB

15. 8 GHz  ADC Technology 0.7 um InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation PK Sundararajan 975 kHz FFT bin size 8 GHz clock rate 65.5 MHz signal 64:1 oversampling ratio Design simple 2nd-order g m -C topology comparator is 87 GHz MSS latch integration by capacitive loads 3-stage comparator, RTZ gated DAC Results 133 dB (1 Hz) SNR at 74 MHz equivalent to ~8.8 bits at 200 MS/s

16. High current density 10 mA/  m 2 T-shaped polysilicon emitter 0.25  m junction wide contact low resistance, high yield Thin intrinsic base: low  b Thick extrinsic base: low R bb Low C cb collector junction collector pedestal CVD/CMP SiO 2 planarization regrown poly extrinsic base High-yield, planar processing high levels of integration LSI and VLSI capabilities SiGe clock rates up to 65 GHz Much more complex ICs than feasible in InP HBT InP HBT must reach higher integration scales or will cease to compete Very strong features of SiGe-bipolar transistors

17. InP vs Si/SiGe HBTs: materials vs scaling advantages Advantages of InP ~20:1 lower base sheet resistance, ~5:1 higher base electron diffusivity ~3:1 higher collector electron velocity, ~4:1 higher breakdown-at same f . Disadvantage of InP: archaic mesa fabrication process Presently only scaled to ~ 1 um (production) large emitters, poor emitter contact: low current density: 2 mA/um 2 high collector capacitance nonplanar device - low yield low integration scales

18. InP HBT limits to yield: non-planar process Emitter contact Etch to base Liftoff base metal Failure modes Yield degrades as emitters are scaled to submicron dimensions Emitter planarization, interconnects

19. MBE growth of Polycrystalline n+ InAs Polycrystalline InAs grown on SiN: Doping = 1.3  10 19 cm -3, Mobility = 620 cm 2 /Vs doping-mobility product 8  10 21 (V s cm) -1 InGaAs lattice matched to InP: Doping = 1.0  10 19 cm -3, Mobility = 2200 cm 2 /Vs doping-mobility product 22  10 21 (V s cm) -1 Polycrystalline InAs has potential as an extrinsic emitter contact Dennis Scott SiGe HBT process: extensive use of non-selective-area poly-Si regrowth Can a similar technology be developed for InP ?

20. Process Flow: Single-poly- regrowth InP HBT Dennis Scott

21. Regrown-Poly-InAs-Emitter HBT Dennis Scott

22. Emitter Regrowth with Buried Base Contact Metal Dennis Scott Buried W/Au base metal under emitter → further reduced R bb Similar to buried WSi base contact process (SiGe, Washio)

23. Submicron Scaling of InP HBTs InP HBTs are a mixed-signal, not a MIMIC technology for MIMICs, sub-0.1-  m InP HEMTs are hard to beat mixed-signal is fiber ICs, ADCs, DACs, digital frequency synthesis these are 1000 -- 40,000 transistor ICs InP HBTs are struggling to compete with SiGe HBT application demands transistor counts near/beyond yield limits large emitter junctions→ high current → power near acceptable limits no decisive speed advantage in relevant circuits: digital logic materials advantages being squandered by inadequate scaling Critically needed for InP HBTs highly scaled process: 0.2  m emitters, 0.4  m collectors highly planar and high-yield fabrication processes small emitter junctions (0.2  m x 0.5  m) for acceptable power