1. Programmable Logic Training Course Project Manager

2. Integration of All Tools Hierarchy Browser allows for direct access to these files Message Window provides error and status messages Toolbar Project Flowchart provides automated data transfer

3. User-Constraints File (UCF) The UCF file is used for entering timing specifications, location constraints, and pin assignments The UCF template contains several examples For more information on proper UCF syntax review a copy of the Xilinx Libraries Guide in the DynaText Browser on the M1 documentation CD

4. Library Manager The command File>Project Libraries enables the user to associate other project libraries To open the Library Manager, click on its icon The Library Manager organizes all macros into libraries and enables the user to delete, copy, and rename macros

5. Programmable Logic Training Course Schematic Editor

6. Adding Symbols To start the Schematic Editor, click on its icon Select-and-Drag mode enables moving symbols, wires, and busses throughout the work area To add symbols to the schematic click on the Symbol Toolbox icon Scroll through the list to find a particular symbol, or enter it’s name at the bottom of the SC Symbols box Replicate symbols by clicking on the symbol while the Symbols Toolbox is still active

7. Wires and Buses To draw wires, click on the Draw Wires icon and click on the two endpoints To draw buses, click on the Draw Buses icon and click on the two endpoints To name a bus, double click on the bus and enter the bus name and width To name a wire, double click on the wire and enter the node name

8. Design Wizard The Design Wizard enables the creation of a symbol before the design is entered After giving the new macro a name, specify the input and output ports Once the symbol information is entered, the State Editor opens a blank page More than one state machine can be made on a single page

9. Adding Hierarchy Tie the project together with a top-level schematic that includes macros from all the Foundation Design Entry Tools As each element of the project is created, make a symbol to represent the macro so that it can be added to the top-level schematic Before a symbol can be created to represent a schematic macro, the macro must contain I/O Terminals that represent ports on the symbol To enter an I/O Terminal, click on its icon, enter the terminal name, select the type of port, place it, and wire it up.

10. Symbol Editor To edit a symbol, click on the Symbol Editor button inside the Symbol Properties dialog box The Symbol Editor can be used to move ports around on a symbol so the schematic looks good

11. LogiBLOX L BX Programmable Logic Training Course Design Entry

12. Net Labels (1) If labels are not given by user, the design entry tool assigns labels. Example: $I152. –Reports are more readable with user defined names. A CLB is named by the net on the output –Flip-Flops are always outputs An IOB is named by the net between the pad and I/O function primitives IN1 IOB IN1 DQ Q2 CLB Q2

13. Net Labels (2) Components especially important to name: –Hierarchical blocks –Flip-Flop controls *Clocks, clock-enables, resets, etc. –Flip-Flop outputs –Both sides of Input and Output buffers –Higher fanout combinatorial signals

14. Use Legal and Readable Names Allowable characters –Alphanumeric: A-Z,a-z,0-9, Underline _, Dash - –Reserved characters *Angle brackets for buses <> *Slash / for hierarchy *Dollar sign $ for instance names Names must contain at least one non-digit Names may be case sensitive –Depends on design entry tool and/or language Avoid using names that correspond to device resources –CLB row/column locations: AA, AB, etc. –IOB pin locations: P1,P2, etc.

15. Hierarchy Guidelines Keep I/O pads on top level Create macros for common functions –Do not save user-defined macros in vendor-supplied library *Future software updates may overwrite the library Do not leave macro inputs floating Net names preserve hierarchical references –SUB2/NET5 There is no limit on the number of levels directly –However, many levels of hierarchy result in long net names

16. Component Name Conventions Common component names, pin names and functions for all families Basic format is –CB4CLE = Counter, Binary, 4 bits, Clear, Load, Enable –FD16RE = Flip-Flops, D-type, 16 bits, Reset, Enable Control inputs are referenced by a single letter –C = asynchronous Clear, R = synchronous Reset –Listed in order of precedence

17. Unified Library (1) The Unified Library contains functions of FIXED SIZE: –Standard functions (XNOR, AND,..etc.) –Flip-Flops / I/O Pad –Three-state buffers –Large functions with standard sizes and options * Example: COMP8 (8 bit Comparator) ACC16 (16bit Accumulator) –Special functions: *High speed, low skew clocks *Boundary Scan Components *Startup Component used for global reset of all flip flops *Oscillator

18. Unified Library (2) Components are customized for each family –Larger functions have a pre-defined layout Unconnected outputs are removed during implementation to avoid unused logic Note: some Synthesizers do not support the entire unified library, and use a unique library. Examples: –Synopsys FPGA Compiler uses the XSI library. Component listing for the XSI library is included in the XSI documentation. –Example: Synplicity does support the Unified library

19. LogiBLOX Library LogiBLOX Library contains templates of VARIABLE SIZE –Templates are expanded or customized *Counters, Adders, Registers, RAM, ROM –LogiBLOX templates have a pre-defined layout –Each generic template can have many implementations *Example: Binary, Johnson, LFSR counters Components are created by expanding a template with the LogiBLOX GUI: –Symbol for schematic capture tool –HDL code for instantiation in a design –Functional simulation model (Behavioral HDL or gate level) –Internal Xilinx design files

20. Use to LogiBLOX in HDL If a LogiBLOX function is inferred (X <= A +B; ): –Behavioral simulation is not needed, there is nothing else to do. –If behavioral simulation will be needed, then execute LogiBLOX to create the simulation model (functional models only). To instantiate a LogiBlox function, or if the synthesis tool doesn’t infer LogiBLOX Automatic: – Use LogiBLOX GUI from command-line : lbgui *Creates an entity or module declaration to in the design The remainder of it chapter will discuss LogiBLOX instantiation

21. Use to LogiBLOX in Schematics Create a schematic symbol and simulation model: –Select a base module type *Example: Counter, Memory, or Shift-register –Customize the module: select bus size and function *Example: Johnson Counter –Select OK Use the LogiBLOX module in the design the same as any other component. –Including functional simulation

22. After completing setup options, create the components to instantiate in the design LogiBLOX Module Selector Specify the component –Bus size from 2 to 32 bits –Bus Structure –Function (Module Type) –Instance name –Any of the inputs or output can be inverted independent *Use Invert or Decode function Select OK Instantiate the component in the design sim2

23. LogiBLOX Simulation The LogiBLOX GUI automatically creates functional simulation models Select simulation Vendor and model type (VHDL, Verilog, Gate Level) as specified earlier Simulation output files are stored in the Project directory (specified in LogiBLOX setup) Within simulator tool, Analyze the timing models