1. Slow Wires, Hot Chips, and Leaky Transistors: New Challenges in the New Millenium Norm Jouppi Compaq - WRL Disclaimer: The views expressed herein are the views of Norm and are not statements by Compaq Computer Corporation

2. Slow Wires l Wires have been slow before (Cray’s computers) l It is not the end of the world l Cray-1 core < 1.5M transistors l Designers need to pay attention l Machine architecture is affected l Opportunity for innovation: l CMP makes more sense l Formerly slow inter-chip MP communication gets faster

3. Hot Chips l Chips have been hot before l E.g., 115W BIPS-0 l It is not the end of the world l Designers need to pay attention l Opportunity for innovation: l Low-power computing (i.e., running off a battery) will not scale well l Now pick only 1 (instead of 2) out of 3: l More function l Lower power l Higher clock speed

4. Background: Leaky MOS Transistors l Two types of leakages l Subthreshold conduction l Leakage between source and drain l Like having a dimmer light switch l Carver Mead has been exploiting for years l Many possible ways to “fix”: SOI, low temp, … l Gate oxide leakage l Leakage between gate and source or drain l Like having a “hot” light switch handle l Over last 25 years, Tox = Le / 45 l Tox = 2.1nm for 0.10um process l Alternative gate dielectrics?

5. Prognosis: Leaky Transistors l Transistors have been leaky before (BJTs) l It is not the end of the world l Designers need to pay attention l Opportunity for innovation: l New CAD tools at the circuit level l Need separate gate processing for memory core l Traditional memory may not scale as well l Exacerbates the power problem

6. Real Problem: Design Complexity l Design team size > 250 people for flagship uP l Design team growing  1/feature size l Designs take longer and have fewer changes l Hennessy’s verification to design team ratio  l ROI negative: l 200people x 3years x 167K$/personyear = 100M$ l NRE/unit = 1K$ for 100,000 units l “Consolidation” has been and will continue l In the number of architectures l In the number of distinct designs

7. Increasing NRE - Example: Mask Cost l A mask set used to cost less than $25K l EUV mask sets may cost >1M$ l Raises barrier to implementation in latest tech l  Standard uP: flagship, DSP, embedded l  Standard RAM: DRAM, Non-Vol, SRAM? l  FPGA’s l ? ASICs l  SOC l  Custom-fit l ? VLSI project chips via maskless tech

8. Summary l + Lots of opportunities for research l - ROIC (human, $) for implementation decreasing l  More and more things will be technically feasible but economically unjustifiable