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Design The Role of EDA in SoC Design HKSTP International Technology Conference January 14, 2003 Dr. Chi-Foon Chan President and Chief Operating Officer.

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Presentation on theme: "Design The Role of EDA in SoC Design HKSTP International Technology Conference January 14, 2003 Dr. Chi-Foon Chan President and Chief Operating Officer."— Presentation transcript:

1 Design The Role of EDA in SoC Design HKSTP International Technology Conference January 14, 2003 Dr. Chi-Foon Chan President and Chief Operating Officer Synopsys, Inc.

2 © 2003 Synopsys, Inc. (2) HKSTP International Technology Conference Agenda Economic Technical Challenges Methodology

3 © 2003 Synopsys, Inc. (3) HKSTP International Technology Conference Agenda Economic Challenges Technical Challenges Methodology

4 © 2003 Synopsys, Inc. (4) HKSTP International Technology Conference IDM $122B IDM $122B Various sources Aprox. Values for 2001 Fabless $10B IP $0.3B Design Design Semiconductor Value Flow in 1996 Systems $851B Embedded SW $0.4B Foundry$5.4B MaskData EDA $2.5B EDA $2.5B Back-End $5.9B Front-End $22B Masks $2.1B Masks $2.1B Materials $4.2B Materials $4.2B Manufacturing

5 © 2003 Synopsys, Inc. (5) HKSTP International Technology Conference Various sources Aprox. Values for 2001 IP $0.9B Design Design Semiconductor Value Flow in 2001 Embedded SW $0.8B MaskData EDA $3.6B EDA $3.6B Back-End $5.6B Front-End $24B Masks $2.3B Masks $2.3B Materials $4.0B Materials $4.0B Manufacturing IDM $106B IDM $106B Fabless $13B Systems $1050B Foundry$9.1B

6 © 2003 Synopsys, Inc. (6) HKSTP International Technology Conference IDM $122B IDM $122B Various sources Aprox. Values for 2001 IP $1.8B Design Design Semiconductor Value Flow in 2006 Embedded SW $1.7B Foundry$31B MaskData EDA $6.1B EDA $6.1B Back-End $10B Front-End $31B Masks $3.7B Masks $3.7B Materials $6.7B Materials $6.7B Manufacturing Fabless $52B Systems $1429B

7 © 2003 Synopsys, Inc. (7) HKSTP International Technology Conference Semiconductor Sales Downturn Source: SIA WSTS 3-mos average, Synopsys October /

8 © 2003 Synopsys, Inc. (8) HKSTP International Technology Conference Semiconductor Sales Downturn Source: SIA WSTS 3-mos average, Synopsys /01

9 © 2003 Synopsys, Inc. (9) HKSTP International Technology Conference Semiconductor Sales Downturn Source: SIA WSTS 3-mos average, Synopsys October

10 © 2003 Synopsys, Inc. (10) HKSTP International Technology Conference Semiconductor Sales Downturn Source: SIA WSTS, Synopsys Worldwide Asia Pacific Percent of Peak Month Sales

11 © 2003 Synopsys, Inc. (11) HKSTP International Technology ConferenceApplicationGraphicsWirelessNetworking WirelessGeometry0.13µ Transistors30M12M 24M12M Cost$10.7M$9.0M$5.7M$10.9M$16.3M Staff-months Escalating Development Costs and Time Source: International Business Strategies, 2002 Sample (Actual) VDSM Projects Average: $10M+, 300+ Staff-months!

12 © 2003 Synopsys, Inc. (12) HKSTP International Technology Conference Process Sophistication Leads to Complex Alliances Fab Process Libraries IP Blocks Tools Flow

13 © 2003 Synopsys, Inc. (13) HKSTP International Technology Conference Semiconductor Partnerships

14 © 2003 Synopsys, Inc. (14) HKSTP International Technology Conference Agenda Economic Overview Technical Challenges Methodology

15 © 2003 Synopsys, Inc. (15) HKSTP International Technology Conference Manufacturability Process antenna effect (PAE) Minimum area rule (MAE) Double cut via End-of-line wire extension Metal filling / wide wire slotting Interconnect Delay Deep Subm Creates Many Problems In  0.18u Wire-to-Wire Cap Dominates (C W >> C S ) CS CS CW CW  0.25  M1 M2 Less Charge M3 Metal 3 Jumper Reduces Metal 1 L M1 Diode Drains Charge Reliability Electromigration Hot electron device degradation Signal Integrity Crosstalk Capacitive coupling Inductive coupling IR (voltage) Drop

16 © 2003 Synopsys, Inc. (16) HKSTP International Technology Conference Challenges in Design Implementation IP Bus Interface MPEG A/D, D/A PL L Sync Arbiter CDI R A M Memory Control Large, Complex Chips Signal Integrity Manufacturability Timing Closure

17 © 2003 Synopsys, Inc. (17) HKSTP International Technology Conference Growing Verification Complexity > 1M lines of HDL code! Lines of Code More Tools and Larger Verification Teams Gates Simulation Cycles Simulation Cycles M10M100M 100B 10T 1995 > 200B Simulation Cycles 70% Verification Design 30%

18 © 2003 Synopsys, Inc. (18) HKSTP International Technology Conference Average Gate Counts By Region Synopsys SNUG Data 2002 Designs tend to be larger in North America (more mP) and tend to be smaller in Asia (more consumer electronics)

19 © 2003 Synopsys, Inc. (19) HKSTP International Technology Conference Most Non-North America Chips Run at <150MHz Synopsys SNUG Data 2002

20 © 2003 Synopsys, Inc. (20) HKSTP International Technology Conference Design Geometries by Region Synopsys SNUG Data % of designs in Asia at.25-micron or larger compared to 22% in Japan and 17% in Europe

21 © 2003 Synopsys, Inc. (21) HKSTP International Technology Conference Most Non-North America Chips Run at <150MHz Synopsys SNUG Data 2002

22 © 2003 Synopsys, Inc. (22) HKSTP International Technology Conference Customers Will Increasingly Converge on Platforms Physical Implementation Design Planning Extraction Physical Verification Mask Synthesis / OPC Languages Assertions and Testbenches Smart Verification Architecture Design Mixed Signal / Analog Verification IP Design Database Timing and Signal Integrity Test Power Physical Synthesis IP Verification Platform Implementation Platform

23 © 2003 Synopsys, Inc. (23) HKSTP International Technology Conference Agenda Economic Technical Challenges Methodology

24 © 2003 Synopsys, Inc. (24) HKSTP International Technology Conference Physics Complexity Design Pressures Courtesy of NVIDIA

25 © 2003 Synopsys, Inc. (25) HKSTP International Technology Conference Challenge: HW/SW Complexity 100MGates EY 10MGates EY 1MGates EY Solutions Solutions 1.Higher level of abstraction System-level toolsSystem-level tools 2. IP design reuse

26 © 2003 Synopsys, Inc. (26) HKSTP International Technology Conference … 80% of the circuitry in SoCs will be acquired, not designed Star IP In-house IP 3rd Party IP CustomerDesigned 50% 80% 95% By

27 © 2003 Synopsys, Inc. (27) HKSTP International Technology Conference IP is at the core of deep sub-micron SoC design methodology Platforms = IP + SLD (HW)

28 © 2003 Synopsys, Inc. (28) HKSTP International Technology Conference IP Reuse: 3 Fundamental Hurdles Efficiently acquiring 3rd-party IP Creating & integrating quality IP Changing the corporate culture

29 © 2003 Synopsys, Inc. (29) HKSTP International Technology Conference IP Reuse: 3 Solutions Choose solid IP partners Design using integrated platform of tools Start right: Use “top down” methodology

30 © 2003 Synopsys, Inc. (30) HKSTP International Technology Conference Agenda Economic Technical Challenges Methodology

31 © 2003 Synopsys, Inc. (31) HKSTP International Technology Conference Current Realities of IC Design EconomicStress Craft advantageous economic ventures Partner with EDA to overcome technical challenges Use “partnered” tools: platforms and IP deal with shrinking geometries and increasing complexities Solution=SmartPartnerships DesignChallengeIncreasingComplexity

32 © 2003 Synopsys, Inc. (32) HKSTP International Technology Conference 2002 EE Times Reader EDA Survey 66% 47% 45% 41% 34% 34% 30% 22% 21% 12% Best integration w/ other vendors’ tools Technology leader today Technology leader in 3 years Clear vision of future Most ethical company Knowledgeable sales reps Well-managed company Best before-sales system support Offers consulting design services Best documentation Best training services Best Web site 9% 20% 8% Attribute in selecting vendor Importance Best after-sales support

33 Design


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