2. INTRODUCTION  Major advantage of digital over analog is the ability to easily store large quantities of digital information and data.  Memory – store information in various forms and purposes such as control information, program instruction, data or as temporary storage.  In a digital computer, the internal memory stores instruction that tell the computer what to do under all possible circumstances so that the computer will do its job with a minimum amount of human intervention.

3. ARCHITECTURE OF MEMORY  Primary memory  as internal memory. Communicate constantly with process.  are RAM and ROM that operate in fast time but smaller capacity.  Any program or data used by the program/process must be reside in the internal memory.  Other name – internal memory, main memory, working memory and semiconductive memory.  Secondary memory (auxiliary mem, disk mem, external memory)  called mass storage with massive amount of data without the need of electrical power.  Operates at slower speed, stores program and data that are not currently being used by CPU.  Typical secondary memory – floppy disk, CD-ROM, magnetic disk, magnetic tape or MBM.  Flash memory with higher speed and lower power consumption, smaller size and non mechanical operation.

6. TYPES OF MEMORY

7. ROM  Hold permanent data and data will not lost when electrical power is turned off.  Normal operation – data can only be read from it. No new data can be written on it.  Major used is in microcomputers as storage of program.  When microcomputer is on, it immediately begin executing the program stored in ROM.  Other usage – any microprocessor controlled equipment or any application where the ratio of read operation is higher then write.  Entering data in ROM is called programming / burning and can only be done in factory.  Types  MROM – also refer as ROM. Programmable only once. At factory.  PROM – programmable only, once. At lab.  RMM – programmed and erased.

8. MROM  Its storage location programmed by the manufacturer according to the customer’s specifications.  Process:  Mask (photographic negative) is used to control the electrical interconnections on the chip.  The mask is expensive, so it is economical for very large quantity of the same ROM.  MROM as Off-the-self devices – programmed with commonly used data such as mathematical table or character generator codes.  Disadvantages  cannot be reprogrammed if the design is changes. Overcome : EPROM.  expensive for lower / small volume application. Overcome : PROM.

11. PROM  Programmed by the programmer not the factory.  Overcome problem with ROM that expensive for small / lower volume applications.  Fusible-link PROMs is user-programmable.  Once programmed, PROM same as MROM.  Also called ‘one time programmable ROMs.’  Electrical construction:  Very similar with MROM but the base terminals are replaced by fusible-link.  User selectively blow any of fuse link to produce logic 0.  Data is programmed or burned into an address location by:  Applying the address to the address pins.  Placing the data at data pins.  Applying high-voltage pulse to a special programming pins.

12.  The process of burning and verifying an PROM done by using PROM programmer attach to a computer.

13. EPROM  Erased and programmed as often as desired.  Once programmed, EPROM acts as ordinary ROM. The programming process involves the application of special voltage level to certain pins for an amount of time.  Electronic circuitry to store data:  MOS transistor with a silicon gate that has no connection (floating gate).  Normal state – each transistor hold logic 1 (transistor off).  Burn state – application of high voltage injects high energy electrons into the floating gate. The traps energy (charges) keeps transistor on permanently even if the power (high voltage) is removed. Now the transistor hold logic 0.  How to select which address to be programmed with data?

14. EPROM  Erased by exposing it to ultraviolet (UV) light through a window in the chip in 15 to 20 minutes.  The UV light produces a photocurrent from the floating gate back to the silicon substrate or in other word, removing the stored charges (energy), turning the transistor off and hold logic 1.  The process will erase all cell (transistor) – disadvantages. Overcome by EEPROM.

15. EEPROM  Using same floating-gate structure as EPROM but with the addition of a very thin oxide region above the drain of MOS transistor. – produces electrical erasability.  Programming :  A charge induces onto the floating gate, remain there (trapped charge) even the power is removed. - (Logic 0)  Erasing :  A charge induces onto the floating gate, removed the trapped charge. - (Logic 1)  The charge mechanism used very low current thus the programming and erasing can be done in circuit. – adv.  Other adv – the ability to electrically erase and rewrite individual bytes. (one address)

16. EAPROM  Allows data alteration at user selected location.  Erasing and reprogramming of data in EAPROM done on board without withdrawing from the socket.  The duration is varied between several ms to several seconds.  Alteration data done by applying electrical pulse.

17. RAM  Contents of RAM will be read or write many times as computer executes program.  Therefore, it require fast read and write cycle times so it will not slow down the operation. – adv.  Disadv – volatile (lose data when power off). Some CMOS RAMs use small amounts of power in the standby mode that they can be powered from batteries.

18. SRAM  Flip-flops that will stay in given state indefinitely, as long as the power in not interrupted.  Available in bipolar or MOS technology.  For higher speed, use BJT RAM.  For higher capacity and lower power consumption, use MOS RAM.

19. BJTNMOS 1. Higher speed than NMOS.1. Lower speed than BJT. 2. Higher capacity than NMOS.2. Lower capacity than BJT. 3. More complex than NMOS.3. Less complex than BJT. 4. Higher power consumption than NMOS. 4. Lower power consumption than BJT.

20. DRAM  Fabricated using MOS technology.  MOS technology - high capacity, low power requirement and moderate operation speed.  1 cell = 1 MOS capacitor sized a few picofarads.  Need refreshing circuitry. Due to periodic recharging memory cells (capacitor). – disadv.  Some DRAM have internal refresh control circuitry by still need time to recharging.  Structure of DRAM is in matrix format.  Larger capacity (4x than SRAM) and lower power consumption. (1/6 to 1/2)– adv.  Lower cost/bit (20%-25%) – adv.

21. DRAMSRAM 1. Higher capacity than SRAM.1. Lower capacity than DRAM. 2. Lower power consumption than SRAM. 2. Higher power consumption than DRAM. 3. Need refresh circuitry.3. No need for refresh circuitry. 4. Used in microcomputer.4. Used in microprocessor controlled instrument and appliances that need small memory capacity requirement. 5. Cheaper than SRAM. (cost/bit) 5. Expensive than DRAM. (cost/bit) 6. Flip-flop6. Capacitor

22. PIN CONNECTION OF RAM  From memory capacity:  Address size  Data size  Pins of memory chip:  Chip capacity : 32 x 4  Data lines / pins (Dn)  4 bits : D 0, D 1, D 2, D 3  Address lines / pins (An)  32 memory location.  Address lines is A 0, A 1, A 2, A 3, A 4  Memory capacity / chip capacity  32 x 4 bits = 128 bits  1 byte = 8 bits, 128 bits = ? 2 n = 32 log 2 n = log 32 n log 2 = log 32  n = log 32 log 2 = 5  A 0, A 1, A 2, A 3, A 4

23. PIN CONNECTION OF RAM  Control (R/W)  READ : data is output from memory, R/W = 0  WRITE : data is input into memory, R/W = 1  Memory Enable (ME)  Enable : ME = 1  Disable : ME = 0  Pins layout:

24. EXAMPLE  A memory chip with capacity of 128k x 8, determine:  Numbers of data lines  Numbers of address lines  Capacity in bit, byte and kbyte  Draw the pins layout block diagram  Determine the capacity in bit, byte and kbyte of the following memory chip:  2k x 4 bits  8k x 6 bits  64k x 16 bits

25. MEMORY MAPPING  A system has the following characteristics:  CPU 8 bit data bus and 16 bit address bus  12kbyte ROM  4kbyte I/O ports  16kbyte RAM  Address size = 2 n = 2 16 = 64k = 65,536 locations with 8 bits data size.

26. MEMORY MAPPING  12kbyte ROM  Address size = 12288 locations  0 – 12287 = $0000 – $2FFF  Address lines = A 0 - A 13  4kbyte I/O  Address size = 4096 locations  12288 – 16383 = $3000 – $3FFF  Address lines = A 0 - A 11  16kbyte RAM  Address size = 16384 locations  16384 – 32767 = $4000 – $7FFF  Address lines = A 0 - A 13  Unused ? 2 n = 12k log 2 n = log 12288 n log 2 = log 12288  n = log 12288 log 2 = 13.58 ~ 14  A 0 – A 13 Start address = 0 End address = 0 + (12288-1) = 12287 Start address = 12288 End address = 12288 + (4096-1) = 16383

27. MEMORY MAPPING  12kbyte ROM  Address size = 12288 locations  0 – 12287 = $0000 – $2FFF  Address lines = A 0 - A 13  4kbyte I/O  Address size = 4096 locations  12288 – 16383 = $3000 – $3FFF  Address lines = A 0 - A 11  16kbyte RAM  Address size = 16384 locations  16384 – 32767 = $4000 – $7FFF  Address lines = A 0 - A 13

28. SOALAN b) Based on the memory pin configuration 2k x 8, determine the numbers of bit for address lines and data lines. c) Build a memory map by referring to the data below: Address bus = 22 bit Data bus = 16 bit ROM = 64k RAM = 512k I/O = 12k Unused = ______

29.  A system has the following characteristics:  16 bit data bus and 22 bit address bus  64k ROM  12k I/O  512k RAM  Address size = 2 n = 2 22 = 4M = 4194304 locations with 16 bits data size.  Start address = $000000 End address = $3FFFFFF

30.  64k ROM  Address size = 65536 locations  0 – 65535 = $0000 – $FFFF  Address lines = A 0 - A 15  12k I/O  Address size = 12288 locations  65536 – 77823 = $10000 – $12FFF  Address lines = A 0 – A 13  512k RAM  Address size = 524288 locations  77824 – 602111 = $13000 – $92FFF  Address lines = A 0 – A 18  Unused  $93000 - $3FFFFF  Address lines = A 0 – A 18

31. ADDRESS DECODER  Accessing memory at one time means we just need to point to a specific location. Therefore, we need to activate only the appropriate memory chip. This is done by address decoder.

32. ADDRESS DECODER  Decoder is a device to accept n bits of input and produce 2 n bits of output.  2 to 4 decoder

33. ADDRESS DECODER  3 to 8 decoder

34. HOW TO DESIGN ADDRESS DECODER``  Identify how many memory chips and its capacity.  Draw the memory map. Memory ChipCapacity of Chip PROM - 02k x 8 PROM - 12k x 8 PROM - 22k x 8 PROM - 32k x 8 Memory location : Start address = $0000 End address = $1FFF Sum of location = $2000 = 8192 location Address lines : 2 n = 8192  n = log 8192 = 13 log 2 Memory: A 0 – A 12 PROM location : 2k = 2 x 1024 = 2048 location Address lines : 2 n = 2048 log 2 n = log 2048 n log 2 = log 2048  n = log 2048 = 11 log 2 Each PROM : A 0 – A 10

35. HOW TO DESIGN ADDRESS DECODER  Address lines table

36. HOW TO DESIGN ADDRESS DECODER  Address lines table

37. COMPLETE ADDRESS DECODER

38. TIMING DIAGRAM  Static RAM Timing  RAM ICs often used as the internal memory of a computer.  This memory chips have to be fast enough to respond to the CPU read and write commands.  However, computer designer has to be concerned with the RAM’s various time characteristics.  To understand the characteristics, we need to examine the timing diagram.

39. READ CYCLE  At t 0, CPU put address at address bus (address input) and R/W* set to 1.  After the address bus is stable, CPU set CS* to 0 (active).  RAM responds by placing the data onto data output (bus data) at t 1.  t ACC = RAM’s access time.  t CO = time from CS* active to data valid in data bus.  At t 2, CS* is set to 1 (inactive).  t 1 to t 3 is the time for CPU take data from data bus.  After t OD, data output will be in Hi-Z.  t RC is time for read cycle complete; t 0 to t 4.

40. WRITE CYCLE  At t 0, CPU put address at address bus (address input).  CPU wait after t AS to set R/W* and CS* to 0 (active).  R/W* and CS* will set low for t w (write time interval).  At t 1, CPU will set data at data bus (data input).  R/W* and CS* need to stay low for t DS (data setup time).  For RAM to write data:  Data at data bus must valid for t DH.  Address at address bus must valid t AH from t 2.  t WC is time for read cycle complete; t 0 to t 4.

41. READ AND WRITE CYCLE  If memory has t RC of 50ns and CPU can read one word at one time, CPU can read 20 millions words / second.

42. DRAM READ/WRITE CYCLES  Timing diagram read and write for DRAM is more complex.

43. READ CYCLE  t 0 : MUX is driven LOW to apply the row address bits (A0 to A6) to the DRAM address inputs.  t 1 : RAS is driven LOW to load the row address into the DRAM.  t 2 : MUX goes HIGH to place the column address (A7 to A13) at the DRAM address inputs.  t 3 : CAS goes LOW to load the column address into the DRAM.  t 4 : The DRAM response by placing valid data from the selected memory cell onto the DATA OUT line  t 5 : MUX, RAS, CAS and DATA OUT return to their initial state.

44. WRITE CYCLE  t 0 : The LOW at MUX place the row address at the DRAM inputs.  t 1 : The LOW at RAS loads the row address into the DRAM.  t 2 : MUX goes HIGH to place the column address at the DRAM input.  t 3 : The LOW at CAS loads the column address into the DRAM  t 4 : Data to be written are placed on the DATA IN line.  t 5 : R/W is pulse LOW to write the data into the selected cell.  t 6 : Input data are removed from DATA IN.  t 7 : MUX, RAS, CAS and R/W are returned to their initial states.