2. HYPER: An Interactive Synthesis Environment for Real Time Applications Introduction to High Level Synthesis EE690 Presentation Sanjeev Gunawardena March 3rd 1998

3. Overview n Some explanation of terms n Architectures for real time applications n Introduction to the Hyper synthesis tool n Hardware Mapper for Hyper n Examples: The wavelet filter n Conclusion n Acknowledgements

4. Some Explanation of Terms n High level synthesis u A task in ASIC development which takes an algorithm, transforms it, assigns operations to suitable units and develops a schedule for the operations that share units. n Layout generators (Silicon compilers) u A tool used in ASIC development after High level synthesis that deals with the placement of hardware units and the routing of wiring between them. n Note: There is often a gap between high level synthesis and layout generators. The synthesis is considered “finished” when a design has been scheduled, but the layout tool expects a completely specified design. n Hardware Mapper u A tool that interfaces the above two steps. It derives a basic implementation of a design from a high level synthesis data representation and “decorates” the implementation with necessary details and presents a fully specified design to a layout generator.

5. Some Explanation of Terms n Signal-flowgraph language u A language used to describe high level digital systems that have little explicit control. u Examples: Silage, Ptolemy, Comdisco, Mentor Graphics n Hardware Mapper

6. Some Explanation of Terms n Control/data flowgraph FIR3 block diagram and flowgraph

7. Some Explanation of Terms n Hardware Description Language u The format in which a design is presented to a layout generator. u This is the output generated by the hardware mapper. u Examples: VHDL, SDL (the structural description language used by the Larger layout generation tools.

8. Architectures for Real Time Applications n Traditional microprocessor architecture u All operations are time-multiplexed on a single, general purpose ALU u Control driven n Hard wired (Data flow driven) architecture u Each operation is represented by a separate hardware unit u Data paths are hard wired to match the algorithmic data flow u Structures are heavily pipelined to achieve high data rates, often equaling or exceeding the maximum achievable clock rate. u Examples: Systolic arrays, speech recognition, and image processing systems. u Programmability is restricted. Results in small controller section. u Design process is very cumbersome. Requires many design iterations. n The Hyper synthesis environment can derive the data path and controller structure starting from a high-level description.

9. The HYPER System n Interactive menu-driven design environment for synthesizing high- performance digital ASICs. n Input to HYPER is a Silage description of an algorithm. n The Silage description is translated into a control/data flowgraph. u Flowgraph represents the same information as the original Silage description, but is easier to manipulate. u The flowgraph can be adorned with details not possible with the Silage description. F Example: timing, area information

10. The HYPER System The HYPER Modules

11. The HYPER System n The selection step u Assigns a unit (or group of units) from a hardware library to each type of node in the flowgraph u The library will contain many implementations of the same block each of which are optimized for performance, area, power consumption etc. n The transformation phase u Performs algorithmic transformations on the flowgraph to achieve a specific result. u Examples: F fixed-coefficient multiplications => series of adds and shifts F algebraic transformations F loop unrolling F retiming and pipelining

12. The HYPER System n The estimation stage u Provides the designer with estimated resource requirements F number of cycles in the critical path F number and type of execution units (EXUs) F number of registers associated with each EXU F number of buses connecting EXUs to registers n The assignment/scheduling step u Assigns each flowgraph node to a specific hardware unit u Derives the number of needed hardware units u NOTE: The clock period and sampling rates must be specified prior to scheduling in order to define the number of cycles available to the system.

13. The HYPER System n The hardware mapping (architecture mapping) stage u maps the flowgraph onto the selected hardware units. F Generates interconnect information F places multiplexers and buffers where needed F defines the FSM and control logic F partitions the datapath u Output of hardware mapper is a group of HDL files. F VHDL F SDL (Structural Description Language used by LargerIV silicon compiler) u After hardware mapping, the system is completely defined.

14. The Hardware Mapper (Overview) n The Hardware Mapper has two main phases u Target independent phase F extracts information from flowgraph and adds details buffers and multiplexers added and control specifications are derived u Target specific phase F generates VHDL or SDL descriptions

15. Resources n High level synthesis tools decide how all operations of an algorithm are performed. n Involves matching a process (e.g. addition) with a pre-designed hardware unit. n The hardware units are organized in libraries. n An index lists all units and their capable operations. n A library may contain more than one unit for the same operation. n It is necessary to select the most appropriate unit (based on speed, area or power efficiency).

16. Resources n A library “data sheet” contains other relevant information for the high level synthesis tool. u Size, speed or power consumption of units u Connectivity information of units u Special unit specific information (such as multiple operation units) n The “data sheet” is the only view HYPER has of a library. It uses the “data sheet” to organize relevant information about hardware units.

17. Resources Library access routines

18. Resources Library Access Routines

19. Resources n A “technology” file is used by HYPER which describes common characteristics of units. (e.g. supply voltage). Technology File

20. Target Independent Phase n First phase of the Hardware Mapper n Translates flowgraph into an intermediate representation to allow subsequent mapping to different target platforms.

21. Target Independent Phase - Architecture Model n HYPER architecture model contains: u Execution units (EXUs) u Register files u Crossbar interconnect network

22. Target Independent Phase - Architecture Model n Register files u Have a single input port => one value written at a time u Dedicated bus exists between output of register and input of EXU it “belongs” to. n Crossbar interconnect network u provides connections from any EXU to register file. u May form different connections at different times. u Implemented by set of dedicated buses, bus drivers and MUXs. u Configured by choosing active bus drivers and selected MUX inputs.

23. HYPER’s Refined Architecture Model n Result of merging basic architecture with crossbar implementation. n A group of muxes, registers, EXUs and buffers connected only by dedicated buses is known as a “cluster”. n Typically, a cluster has only one EXU. n A cluster can have unlimited EXUs.

24. Target Independent Phase - Register Selection n Mapper considers only area when selecting register hardware. n The Mapper has four types of registers. u Register files F contain one or more registers F can be read/write or read only F can address one location for reading and one for writing in one clock cycle F all registers in the file have the same bit width (at least 1-bit) u Single registers with tri-stated outputs F can store one value at a time F read/write or read only F can be both read and written in one clock cycle F register must have a parameterizable bit width (at least 1-bit) F can be connected in parallel with other registers of this type to create a register file

25. Target Independent Phase - Register Selection u Single Registers without tri-stated outputs F can store one value at a time F read/write or read only F can both be read and written in a clock cycle F cannot be connected in parallel with other registers. F Can only be used when a HYPER design requires a register file with a single location. u Flip-flops F single-bit standard cell registers F D-FFs F rising edge triggered

26. Target Independent Phase - Register Selection Process n Determine the size of each Hyper register file, as annotated in the flowgraph. n Determine which register or combination offers a better solution u Done on a per-register-file basis u Smallest viable solution is chosen as the optimal

27. Target Independent Phase - Flowgraph Translation n Hardware mapper takes a scheduled flowgraph and extracts the necessary information from it.

28. Target Independent Phase - Bus Merging n Hardware mapper is capable of minimizing the number of physical buses in a design (optional). n Area of bus merged design is 40-60% smaller than non bus merged implementation. n Bus merging routines u Fanin bus merging u Fanout bus merging u Global bus merging Bus merging flowchart

29. Target Independent Phase - Bus Merging n Fanin bus merging u joins all input buses of a register file to a single bus n Fanout bus merging u Joins all output buses of an EXU to a single bus n Global bus merging

30. Target Independent Phase - Bus Merging Example n Seventh order IIR filter was generated by Hyper n Critical path - 10 clock cycles (16 clock cycles available time) n Implementation u 2 shifters u 1 adder u 1 subtractor n Results:

31. Target Independent Phase - Buffers and Multiplexers n After bus merging, buffers and muxes are added to the design n Buffer selection u Needed to drive large loads of buses. u Can be turned ON or OFF so that one buffer can drive a bus at a given time. u Selection routine inserts a simple buffer between EXUs and buses when the bus is driven by one EXU. u Selection routine inserts a tri-state buffers when multiple EXUs are driving the same bus.

32. Target Independent Phase - Buffers and Multiplexers n Mux selection u Always placed at the inputs of register files. u Mux servers at a bus selector for the register file with which it is associated. u Selection routines recognize how many buses are connected to the input of a register file. u Examples: F register file has one bus connected to input => no mux assigned F register file has two buses connected to input => 2:1 mux assigned

33. Target Independent Phase - Control Generation n Last step in the target independent phase of hardware mapper

34. Target Independent Phase - Control Generation n State transition graph generation (from flowgraph) u Keeps track of all the states and the operations that must take place during those states. u Determines which control signals will be used for control flow (branches, jumps etc) u Two types of control flow are supported F sequential flow (does not require any control signals to flow from the datapath to the controller) F simple loops (requires that the controller can receive feedback from the datapath to determine when or if to branch. n Example:

35. Examples - The Wavelet Filter n Contains a high pass and a low pass FIR filter. n High and low pass sections share constant coefficients for their 14 taps.

36. Examples - The Wavelet Filter n Implementation using 22 clocks/sample No bus mergingWith bus merging Buses:155 Muxes:54 Buffers:186 Registers:5656 Actual layout:7.0 mm 2 4.6 mm 2 Mapper predicted area:5.2 mm 2 3.6 mm 2

37. Examples - The Wavelet Filter Implementation of the wavelet filter without bus merging

38. Examples - The Wavelet Filter Implementation of the wavelet filter with global bus merging

39. Examples - The Wavelet Filter (conclusion) n The mapper’s area predictions are too small because the area of control logic and control wiring is not known at the time the prediction is made. n Bus merging is clearly desirable when chip area is a concern. Fir this example, a savings of 2.4 mm 2 was realized.

40. Conclusion n The Hyper synthesis environment can be effectively used to derive the data path and controller structure from a high level description (Silage) n The Hyper system is comprised of several functional blocks which include selection, transformation, estimation, assignment/scheduling and hardware mapping. n The hardware mapper takes the scheduled flowgraph generated by Hyper and maps it to specific hardware units described in a library, generating an HDL output. The hardware mapper is the interface between the high level synthesis tool (Hyper) and the silicon compiler. n The real time example shows that the design can be optimized for users specific needs (area, speed, etc)

41. Acknowledgments n The bulk of the material for this presentation was obtained from Ole Bentz’ (University of California, Berkley) masters thesis titled “A Hardware Mapper for the Hyper High Level Synthesis System.” n http://infopad.eecs.berkeley.edu/~bentz/MastersReport/index.ht ml