1. 11/22/2005SSST: CS130 F. Hadziomerovic1 Review 1.Data types and operations: Numbering systems: unary, binary, octal, decimal hexadecimal Binary addition and substraction using 2’s complement arithmetic Logical operation: AND, NOT, OR. Floating point format and ASCII format for input/output 2.Digital Logic: Boolean algebra and implementation with Combinational Circuits Implementation of Boolean functions with PLAs Feedback and RS flip-flop. Gated D flip-flop Register as array of D flip-flops Memory as array of registers: address space and addressability Sequential Circuits (FSM): state diagrams, block diagram, race condition and master-slave flip-flop. FSM implementation with micromemory. 3.Von Neumann Concept: CPU, Memory, I/O CPU: ALU, Control Unit Instructions (ISA): format, addressing modes Instruction executions: fetch cycle, execution cycle Computer Architecture (Data Path) around single bus, signals Micro-architecture and FSM of the LC-3 computer 4.Programming Machine language programming: LC-3 editor, LC-3 simulator Problem solving and structured programming Common bugs and debugging

2. 11/22/2005SSST: CS130 F. Hadziomerovic2 Data types and operations: Numbering systems: unary, binary, octal, decimal, hexadecimal Floating point format and ASCII format for input/output ASS#1 Question 2 (IEEE floating point standard): transform the speed of light c = 300,000,000 m/sec into the floating point number. Show your steps. (You may use approximation when converting from base 10 to base 2) (25 points) 300,000,000 = 1.117587*228 = (1 + 0.00011110000110100011000)*2155-127 = 0 100 1101 1000 1111 0000 1101 0001 1000 =x 4D8F0D18 Midterm Question 1:Write in binary the maximum positive number in floating point binary format. (5 points) 0 11111110 11111111111111111111111 = x7F7FFFFF What is the value of this number (to express it you can use powers of 2)? (5 points) 2 127 (1 + 1 – 2 -23 ) ~ 2 128 If the same number would be interpreted as 2 complement binary format what will be the value? (5 points). 2 31 – 1 – 2 23 ~ 2 31 Write 0 (zero) in floating point format and express it in hexadecimal. (5 points) 0 00000000 00000000000000000000000 = x00000000 Question 1: In a numbering system with base N what are the values of single digit? (5 points) 0 1 2 3 4 … N-1 Which numbering system base was the closest to Roman way of writing numerals? (5 points) 1 How many different numbers can be represented in floating point format? (5 points) 2 32 In floating point format the numbers are not evenly distributed on the numbering line. What is the biggest and the smallest difference between two consecutive numbers? (5 points) Biggest = 2 104 smallest = 2 -149

3. 11/22/2005SSST: CS130 F. Hadziomerovic3 Digital Logic: Boolean algebra and implementation with Combinational Circuits Implementation of Boolean functions with PLAs Ass #1: Question 3 (combinational circuit): Given the following truth table, generate the gate-level logic circuit, using the implementation algorithm referred to in Section 3.3.4. (25 points) Z CBACBA A B C Z 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0

4. 11/22/2005SSST: CS130 F. Hadziomerovic4 X ABCABC Y Any logical functions (here X and Y) can be implemented by two levels circuits: ANDs and ORs. Digital Logic (cont.): Implementation of Boolean functions with PLAs

5. 11/22/2005SSST: CS130 F. Hadziomerovic5 c a b p CC a b p 0 0 stable 0 1 0 1 0 1 1 1 x a p b time c b a p x x 1 0 0 1 0 1 a: 1 0 a: 0 1 b: 1 0 b: 0 1 c b a x x 1 0 0 1 0 1 p = a + b’c b’ p c a p’ a b p Digital Logic (cont): Feedback and RS flip-flop.

6. 11/22/2005SSST: CS130 F. Hadziomerovic6 Digital Logic (cont): Gated D flip-flop Register as array of D flip-flops One bit register = memory cell WE = Clock pulse in bit gate RS out bit WE b5b5 b4b4 b3b3 b2b2 b1b1 b7b7 b6b6 b0b0 Eight bit register

7. 11/22/2005SSST: CS130 F. Hadziomerovic7 Ass#2 Question 2 Incrementer: PC increments by 1 every fetch cycle. Draw block diagram (5 points), truth table (5 points), and detailed implementation (10 points) of one bit cell with a single line signal: 1 – increment, 0 – do not increment. Digital Logic (cont): Register as array of D flip-flops cl PC incrementer c = incr clock 1 0 Incr. truth table Di Ci Do Co 0 0 0 1 1 0 1 0 1 1 DoDo cici coco 0 1 DiDi

8. 11/22/2005SSST: CS130 F. Hadziomerovic8 Digital Logic (cont): Memory as array of registers: address space and addressability address decoderaddress decoder N address lines (bus) address space = 2 N M data lines (bus) adressability = M WE memory 0 memory 1 memory 2 memory 3 memory 4 memory 5 memory 6 memory 7

9. 11/22/2005SSST: CS130 F. Hadziomerovic9 Digital Logic (cont): Memory details word select word WE address write enable input bits output bits

10. 11/22/2005SSST: CS130 F. Hadziomerovic10 Digital Logic (cont): Memory as array of registers: address space and addressability Midterm Question 3: Suppose you have three memory blocks 1 kB each. Consequently each block has 10 address bits (wires), 8 data bits (wires), 1 r/w bit (wire), and 1 enable bit (wire). If enable bit = 1 memory output wires (data) are active, else they are high impedance. Connect these blocks to the MAR and MDR to have 3 kB memory capacity. (15 points) A10 A11 A0-A9 and r/w E Data E E 1 KB 8 11

11. 11/22/2005SSST: CS130 F. Hadziomerovic11 Ass#1: Question 4 (sequential circuit): given the state diagram below implement sequential circuit with D flip-flops: draw block diagram, state table, and implement combinational circuit. (25 points) Digital Logic (cont): Sequential Circuits (FSM): state diagrams, block diagram, race condition and master-slave flip-flop. C State Current next I B C B+ C+ 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 1 x x 1 1 1 x x combinati- onal circuit 1 1 01 00 10 0 0 1 0 I B D D cl B+ C+ C B I B+ I I C B B

12. 11/22/2005SSST: CS130 F. Hadziomerovic12 Digital Logic (cont): FSM implementation with micromemory. Ass#2 Question 1 Microsequencing: Implement the traffic danger sign from 3.6.4. (FSM is in Fig.1) using micromemory and microsequencer given below (Fig. 2). How many flip-flops do you need (minimum)? (10 points).Write the micromemory content (20 points). Draw detailed microsequencer (10 points), b. micromemory. All Off 1,2 On 1,2,3,4 On All On 0 0 1 1 0 1 0, 1 00 01 1011 SW Microsequencer clock Micromemory microinstruction lamps SW Fig. 1. Fig. 2. Next state current state =address 1 0 SW 00 From micro instruction Next state a. two flip-flops. lamps Address next st 1 2 3 4 5 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 c. microsequencer.

13. 11/22/2005SSST: CS130 F. Hadziomerovic13 Digital Logic (cont): FSM implementation with micromemory. Midterm Question 4: Consider the sequential circuit in figure below (textbook Fig 3.43). Fill in the next state table. (5 points). Draw the state diagram. (5 points). Implement the same circuit using micromemory and give the micromemory content. (15 points). X Z S0S0 S1S1 D0D0 D1D1 Clock 1011 01 X=0, 1 X=0 X=0,1 X=1 Addr next S 0 S 1 D 0+ D 1+ Z X’ 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 S0S0 S1S1 D0D0 D1D1 Clock X X’ Micro mem D1+ D0+D0+ Z X S 0 S 1 D 0 D 1 Z 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 00

14. 11/22/2005SSST: CS130 F. Hadziomerovic14 OP ADDRESS PC MDR ACC ALU GOTO F E F E MARMAR CPU I/O MEMORY Von Neumann Concept Instruction executions: fetch cycle, execution cycle Instructions (ISA): format, addressing modes ACC - Accumulator Register ALU - Arithmetic Logic Unit CPU - Central Processing Unit E - Execution phase F - Fetch phase I/O - Input Output (Terminal) MAR - Memory Address Register MDR - Memory Data Register OP - Instruction operation PC - Program Counter

15. 11/22/2005SSST: CS130 F. Hadziomerovic15 Von Neumann Concept (cont.): Instructions (ISA): format, addressing modes Ass#2 Question 4 Instruction Fields: Assume that memory in Question 3 is 10 bits wide. and instructions use only direct memory addressing mode (IR address field is the operand address) without bit extensions. What is the maximum memory capacity? Briefly explain your answer. (15 points). REG OP OPERAND ADDR 2 bits for: LD register, add, sub, ST. 1 bit for register: 0 – A, 1 – B And remaining 7 bits for operand address. Therefore max memory capacity = 2 7 = 128. Addressing modes: immediate (operand in instruction), register (reg in instruction, operand in register) Memory (memory address/offset in instruction, operand in memory): PC-relative, Base+offset, indirect.

16. 11/22/2005SSST: CS130 F. Hadziomerovic16 Von Neumann Concept (cont.): Instructions (ISA): format, addressing modes Addressing modes: immediate (operand in instruction), register (reg in instruction, operand in register) Memory (memory address/offset in instruction, operand in memory): PC-relative, Base+offset, indirect.

17. 11/22/2005SSST: CS130 F. Hadziomerovic17 Computer Architecture: Computer Architecture (Data Path) around single bus, signals Ass#2 Question 3 Data Path: assume very simple computer with two registers A and B, that can perform operations below. A <- M[IR], B <- M[IR], A <- A + B, A <- A – B, M[IR] <- A Draw the necessary data path (around single bus architecture) to carry these operations by showing registers (including PC,IR, MAR, and MDR), adders, gates, etc., data paths and control signals (with arrowheads not filled in). (25 points) PC PCon A Aon LDA LDB B MAR LDMAR Memory MDR MDRon LDMDR r w IR IRon inv invert +1 ALU bus LDIR

18. 11/22/2005SSST: CS130 F. Hadziomerovic18 Computer Architecture (cont.): Computer Architecture (Data Path) around single bus, signals Micro-architecture and FSM of the LC-3 computer Midterm Question 2: LC-3 architecture is built around a single bus (ref. textbook Fig. C.3). How many wires are in the bus? (5 points) 16 List the registers that the bus transfers data from/to? (5 points) PC, IR, R0 to R7, MAR, MDR If you need to transfer data from source to destination register which signals should you activate (at the same time)? (5 points) GateSource and LD.Destination Midterm Question 2: LC-3 architecture is built around a single bus (ref. textbook Fig. C.3). How many wires are in the bus? (5 points) 16 Can you have LC-3 architecture without using MAR and MDR? How many wires will buss have to have? (5 points) 32 In this architecture, which signals you need to activate to fetch an instruction? (5 points) PC.on, LD.IR and r

19. 11/22/2005SSST: CS130 F. Hadziomerovic19 Programming Machine language programming: LC-3 editor, LC-3 simulator Midterm Question 5: Consider the program below: Translate the program to binary form (10 points). Interpret instructions in mnemonic form (10 points). What does the program do? (5 points) Address Contenta. Binaryb. Mnemonic x3000 x54A0 0101 0100 1010 0000AND R2, R2, #0 x3001x14AA0001 0100 1010 1010 ADD R2, R2, #10 x3002xE2FD1110 0010 1111 1101LEA R1, x3100 x3003xF0231111 0000 0010 0011TRAP IN x3004x70400111 0000 0100 0000STR R0, R1, #0 x3005x12610001 0010 0110 0001ADD R1, R1, #1 x3006x14BF0001 0100 1011 1111ADD R2, R2, # -1 x3007x03FB0000 0011 1111 1011BRp x3003 x3008xF0251111 0000 0010 0101TRAP HALT c. Program stores 10 input characters into 10 memory locations starting with x3100. Question 5: Consider the program below: Translate the program to binary form (10 points). Interpret instructions in mnemonic form (10 points). What does the program do? (5 points) Address Contenta. Binaryb. Mnemonic x3000x52600101 0010 0110 0000AND R1, R1, #0 x3001x126A0001 0010 0110 1010ADD R1, R1, #10 x3002xE40D1110 0100 0000 1101LEA R2, x3010 x3003x60800110 0000 1000 0000LDR R0, R2, #0 x3004xF0211111 0000 0010 0001TRAP OUT x3005x14A10001 0100 1010 0001ADD R2, R2, #1 x3006x127F0001 0010 0111 1111ADD R1, R1, #-1 x3007x0BFB0000 1011 1111 1011BRnp x3003 x3008xF0251111 0000 0010 0101TRAP HALT c. Prints the ASCII content of 10 consecutive memory locations starting with x3010.

20. 11/22/2005SSST: CS130 F. Hadziomerovic20 Programming (cont.): Problem solving and structured programming: Example page 139 Common bugs and debugging Number of occurences (count): R2 <- 0 Input char from keyboard into R0: trap 23 Initialize pointer: R3 <- starting file address R1 ?= EOT no yes R0 ?= R1 no Incr.count R2<-R2+1 Incr.point R3<-R3+1 Get char from file: R1 <- M[R3] yes Prepare output: R0 <- R2 + x30 Display char: trap 21 halt: trap 25

21. 11/22/2005SSST: CS130 F. Hadziomerovic21 Mnemonic program that displays how many times the keyed character shows in a file X3000 AND R2,R2,#0 ; R2 <- 0 x3000 0101010010100000 x54A0 x3001Trap x23 ; input charx3001 1111000000100011 xF023 x3002LD R3, start filex3002 0010011000001110 x460E X3003LDR R1,R3,#0 ; get charx3003 0110001011000000 x62C0 X3004ADD R4, R1, #-4 ; ‘eot’ = 4x3004 0001100001111100 x187C X3005BRz x300Dx3005 0000010000000111 x0407 X3006NOT R1x3006 1001001001111111 x927F X3007ADD R1,R1,#1x3007 0001001001100001 x1261 X3008ADD R1, R1, R0x3008 0001001001000000 x1240 x3009BRnp, x300Bx3009 0000101000000001 x0A01 x300AADD R2,R2,#1x300A 0001010010100001 x14A1 x300B ADD R3, R3,#1x300B 0001011011100001 x16E1 x300CBRnzp x3003x300C 0000111111110110 x0FF6 x300DLD R0, x3012x300D 0010000000000100 x2004 x300EADD R0, R0, R2 ; ASCII countx300E 0001000000000010 x1002 X300FTRAP x21 ; display R0x300F 1111000000100001 xF021 X3010TRAP x25 ; haltx3010 1111000000100101 xF025 X3011start address of a filex3011 0011000000010011 x3013 X30120030 ; ASCII_offset x3012 0000000000110000 x0030

22. 11/22/2005SSST: CS130 F. Hadziomerovic22 Assembly language.ORIG x3000 AND R2, R2, #0 ; R2 is a counter initialize to 0 LEA R3, PTR; PTR is start address of a file Trap x23 ; get input character to R0 input char AGAINLDR R1, R3, #0 ; get char from a file ADD R4, R1, #-4 ; check the end of file ‘eot’ = 4 BRz OUTPUT NOT R1, R1 ADD R1, R1, #1 ADD R1, R1, R0; file char vs input char BRnp NEXT ADD R2, R2, #1; char found increment counter NEXTADD R3, R3, #1; increment pointer in a file BRnzp AGAIN OUTPUTLD R0, ASCII; ASCII offset ADD R0, R0, R2 ; count in ASCII TRAP x21 ; display count (R0) TRAP x25; halt ASCII.FILLx0030 ; ASCII_offset PTR.STRINGZ "Hello world"; file.END

23. 11/22/2005SSST: CS130 F. Hadziomerovic23 Assembly format label opcode operands ; comment AGAIN LDR R1, R3, #0 ; get char from a file Pseudo-ops (Assembler Directives).ORIG x3100; (x – hexadecimal, # - decimal) PC = x3100.FILL #10; this location will be filled with decimal 10.BLKW 11; 11 successive locations are reserved.STRINGZ “Hello” ; 5 successive locations are loaded with char string.END; end of assembly program.EXTERNAL; cross-reference

24. 11/22/2005SSST: CS130 F. Hadziomerovic24 How assembler works.ORIG x3000 AND R2, R2, #0 ; initialize counter R2 to 0 LEA R3, PTR; PTR is start address of a file Trap x23 ; get input char to R0 AGAINLDR R1, R3, #0 ; get char from a file ADD R4, R1, #-4 ; check the end of file ‘eot’ = 4 BRz OUTPUT NOT R1, R1 ADD R1, R1, #1 ADD R1, R1, R0 ; file char vs input char BRnp NEXT ADD R2, R2, #1; char found incr counter NEXTADD R3, R3, #1; increment pointer in a file BRnzp AGAIN OUTPUTLD R0, ASCII; ASCII offset ADD R0, R0, R2 ; count in ASCII TRAP x21 ; display count (R0) TRAP x25; halt ASCII.FILL x0030 ; ASCII_offset PTR.STRINGZ "Hello world"; file.END Two passes: First pass: Make a symbol table SymbolAddress AGAINx3003 NEXTx300B OUTPUTx300D ASCIIx3011 PTRx3012 Second pass: Translate mnemonic using symbol table x3000 0101 010 010 1 00000 x3001 1110 011 000010000 (x3012 – x3002 = x10) X3002 1111 0000 00100011 X3003 0110 001 011 000000 X3004 0001 100 001 1 11100 X3005 0000 010 000000111 (x300D – x3006 = x07) X3006 1001 001 001 111111 X3007 0001 001 001 1 00001 X3008 0001 001 001 0 00 000 Etc.

25. 11/22/2005SSST: CS130 F. Hadziomerovic25.EXTERNAL ; beyond a single assembly program 1..ORIG x3000 2.AND R2, R2, #0 ; initialize counter R2 to 0 3.LD R3, PTR; PTR is start address of a file 4.Trap x23 ; get input char to R0 5.AGAINLDR R1, R3, #0 ; get char from a file 6.ADD R4, R1, #-4 ; check the end of file ‘eot’ = 4 7.BRz OUTPUT 8.NOT R1, R1 9.ADD R1, R1, #1 10.ADD R1, R1, R0 ; file char vs input char 11.BRnp NEXT 12.ADD R2, R2, #1; char found incr counter 13.NEXTADD R3, R3, #1; increment pointer in a file 14.BRnzp AGAIN 15.OUTPUTLD R0, ASCII; ASCII offset 16.ADD R0, R0, R2 ; count in ASCII 17.TRAP x21 ; display count (R0) 18.TRAP x25; halt 19.ASCII.FILL x0030 ; ASCII_offset 20..EXTERNAL STARTofFILE 21.PTR.FILL STARTofFILE 21..END 1..ORIG x4000 2.STARTofFILE.STRINGZ "Hello World" 3..FILL x04 4..END Assembler does not know STARTofFILE location and.EXTERNAL tells it that this will be linked later. When linker is called then cross-references (unresolved labels) are filled in from other Symbol Tables.

26. 11/22/2005SSST: CS130 F. Hadziomerovic26 Memory mapped Input/Output (I/O) x0000 xFE00 xFDFF xFFFF DDR 15 8 7 0 DSR KBDR 15 14 0 xFE06 xFE04 15 8 7 0 xFE02 xFE00 KBSR 15 14 0 KBSR[15] = 1; new char in KBDR DSR[15] = 1 ; DDR is ready for new char. memory I/O registers

27. 11/22/2005SSST: CS130 F. Hadziomerovic27 Memory mapped Input/Output (I/O) architecture Memory E Address Control MIO.EN KBDR KBSR DSR DDR MAR MDR LD.MAR GateMDR R.W 2 LD.MDR bus keyboard display DDR 15 8 7 0 DSR KBDR 15 14 0 xFE06 xFE04 15 8 7 0 xFE02 xFE00 KBSR 15 14 0 KBSR[15] = 1; new char in KBDR DSR[15] = 1 ; DDR is ready for new char. set re set test

28. 11/22/2005SSST: CS130 F. Hadziomerovic28 I/O service routines DDR 15 8 7 0 DSR KBDR 15 14 0 xFE06 xFE04 15 8 7 0 xFE02 xFE00 KBSR 15 14 0 KBSR[15] = 1; new char in KBDR DSR[15] = 1 ; DDR is ready for new char. ; input service routine STARTLDI R1, A BRzp START LDI R0, B BRnzp NEXT_TASK A.FILL xFE00 B.FILL xFE02 ;keyboard echo STARTLDI R1, KBSR BRzp START LDI R0, KBDR ECHOLDI R1, DSR BRzp ECHO STI R0, DDR BRnzp NEXT_TASK KBSR.FILL xFE00 KBDR.FILL xFE02 DSR.FILL xFE04 DDR.FILL xFE06 ; output service routine STARTLDI R1, A BRzp START STI R0, B BRnzp NEXT_TASK A.FILL xFE04 B.FILL xFE06

29. 11/22/2005SSST: CS130 F. Hadziomerovic29 LC-3 keyboard input routine 1.Start ST R1, SaveR1 ; save registers 2. ST R2, SaveR2 3. ST R2, SaveR2 4. LD R2, Newline 5.L1 LDI R3, DSR 6. BRzp L1 ;loop until display ready 7. RTI R2, DDR ;display newline 8. LEA R1, Prompt 9.Loop LDR R0, R1, #0 10. BRz Input 11.L2LDI R3, DSR 12. BRzp L2;wait for monitor ready 13. STI R0, DDR ;write next prompr char. 14. ADD R1, R1, #1 15. BRnxp Loop 16.InputLDI R3, KBSR 17. BRzp Input;wait for char 18. LDI R0, KBDR;get input char 19. L3LDI R3, DSR 20. BRzp L3;wait for monitor 21. STI R0, DDR;display char 22.L4LDI R3, DSR 23. BRzp L4;wait for monitor 24. STI R2, DDR;move cursor to new line 25. LD R1, SaveR1 26. LD R2, SaveR2 27. LD R3, Save R3 28. BRnzp Next_Task 29.SaveR1.BLKW1 30.SaveR3.BLKW1 31.DSR.FILLxFE04 32.DDR.FILLxFE06 33.KBSR.FILLxFE00 34.KBDR.FILLxFE02 35.Newline.FILLx000A 36.Prompt.STRINGZ “Input a character>” Critique: Loops L1, L2, L3, L4 wait until display ready. Loop Input waits until char available – gross. For instance 1 char per sec means wait of 1 million instruction executions – waste of computer time. Solution: interrupt: processor is interrupted only when the character is ready. Generally processor is interrupted when peripheral device needs service.

30. 11/22/2005SSST: CS130 F. Hadziomerovic30 Interrupt DSR 15 14 13 0 xFE04 xFE00 KBSR 15 14 13 0 PL of running program PL1 PL2 Priority decision Other device priorities Interrupt line to processor Interrupt is tested before every FETCH cycle. If interrupt priority is larger than running program priority Interrupt is granted: 1. PC and PSR are saved on stack and jump is made to interrupt service routine. 2. Interrupt service routine must end up with RTI (Return from Interrupt) instruction which loads PC and PSR back from the stack. running program interrupt ISR (Interrupt Service Routine) RTI running program Jump to ISR Return from ISR