1. NS Training Hardware

2. NS9750 Ethernet Block

3. Overview
Ethernet Module consists of a Media Access Controller (MAC) and Ethernet Front End module
To External PHY
Ethernet MAC
Ethernet Front End
Module
AHB BUS
(To Memory)

4. MAC 10/100Mpbs Dual-Speed Operation
Meets ISO/IEC and IEEE 802.3u specifications
Full and Half-Duplex operation
Station address logic (SAL)
Address Filtering.
Broadcast, Unicast, Multi-cast, Multi-cast w/Hash table.
Statistics Module (New in 9750); completely enhanced when compared to the old chip sets with richer counter set over 30.
Internal Loopback
Programmable MII or RMII (New in 9750) PHY interface
MII Management interface to control PHY
Supports MII Management Interface clock of up to 12.5Mhz (New in 9750)

5. Ethernet Front-End Module (EFE)
Provides control functions to the MAC
2KB RX Data FIFO and 256B TX Data FIFO
Separate RX and TX DMA Controllers
Internal storage for 64 TX Buffer Descriptors (New in 9750)
Supports 4 rings of RX Buffer Descriptors (in external memory)
Power Down Mode (wake on first packet) (New in 9750)
Supports big or little endian modes on AHB bus

6. NS9750 PHY Connections
1.RX_ER is an optional signal per the RMII specification. Pull-down if not being used.

7. Example Ethernet Setup Procedure
Take EFE and MAC modules out of reset
Configure the external PHY via the MII Management registers in the MAC
Configure the MAC (e.g. full-duplex,MII PHY,append TX CRC,etc.)
Configure Station Address Logic (e.g. load station address,accept Broadcast packets)
Configure Statistics Module (e.g. counters clear on read)
Setup 4 rings of RX buffer descriptors in external memory. Rings are distinguished by maximum packet length supported (e.g. 64, 128, 256, and 2K bytes)
Setup multiple TX buffer descriptors in TX Buffer Descriptor RAM in EFE. Packets can use several linked descriptors.
See example in Hardware Users Guide for more detail.

8. Example Ethernet Setup Procedure
Load TX packet in external memory pointed to by TX Buffer Descriptor(s)
Enable DMA operation for both RX and TX DMA Controllers
Enable MAC to RX packets
Wait for RX and TX interrupts (all interrupts can be disabled individually)
Per-ring RX interrupt driven when entire RX packet stored in external memory
TX interrupt driven when TX packet successfully transmitted
Both RX and TX Buffer Descriptors updated at end of packet with status information and packet length.
See example in Hardware Users Guide for more detail.

9. Hints & Kinks
For RMII PHY applications do I connect the REF_CLK pin of the PHY to the RX_CLK input of the NS9750?
RMII PHYs do not provide a clock to the MAC like MII PHYs. A 50Mhz external oscillator is required. It is connected to the REF_CLK input of the RMII PHY and the RX_CLK input of the NS Take care to provide a clean clock signal to both inputs.

10. MII PHY Interface Timing
rx_clk and tx_clk 25Mhz for 100Mbps or 2.5Mhz for 10Mbps

11. RMII PHY Interface Timing
ref_clk used for both RX and TX interfaces and connected to rx_clk of NS9750.
ref_clk is 50 Mhz for both 10 and 100 Mbps. Data changes every 10th clock for 10Mbps mode.
crs is a dual-use signal that performs the function of carrier sense and rx data valid. It is the crs function while rxd[1:0] is ’00’ and rx_dv when rxd[1:0] transitions to ’01’ during preamble.