3 OverviewThe LCD Controller provides an interface to a STN or TFT LCD Panel. Display data is DMAed from external memory to the LCD controller.To LCD PanelLCD ControllerAHB BUS(To Memory)
4 LCD ControllerSupports both monochrome and color, single- and dual-panel Super Twisted Nematic (STN) LCD panelsSupports 18 and 24-bit Thin Film Transistor (TFT) LCD color displaysSTN mode supports up to 15 gray-levels for monochrome and 3375 colorsTFT mode supports up to 16M colorsSupports all popular display resolutions up to 1024x768 maximum256 entry, 16-bit palette RAMMonochrome STN supports 1,2, or 4 bits-per-pixel via palette RAM
5 LCD ControllerColor STN supports 1,2,4, or 8 bits-per-pixel via palette RAMTFT supports 1,2,4,or 8 bits per-pixel via palette RAM; 16 and 24 bits per pixel directLCD timing programmableAHB DMA engine transfers display data from external memory to dual 64x32 FIFOsSupports big and little endian pixel format, as well as WinCELCD panel clock can either be generated internally from the AHB clock or provided via an external oscillator
6 LCD Controller Programmable Parameters Horizontal front porchHorizontal back porchHorizontal sync pulse widthNumber of pixels per lineVertical front porchVertical back porchVertical sync pulse widthNumber of lines per panelNumber of panel clocks per lineSignal polarityAC panel biasPanel clock frequencyNumber of bits-per-pixelDisplay type (STN mono/color or TFT)STN 4 or 8 bit interfaceSTN dual or single panelPixel format (little-endian, big-endian or WinCE)Interrupt generation event
7 LCD Panel Interface Signal Description CLPOWER LCD panel power enable CLLPLine sync pulse (STN) or horizontal sync pulse (TFT)CLCPLCD panel clockCLFPFrame pulse (STN) or vertical sync pulse (TFT)CLACAC bias drive (STN) or data enable (TFT)CLD[23:0]LCD panel dataCLLELine end signal
8 LCD Setup ProcedureSetup horizontal timing parameters for LCD panel (e.g. front porch, back porch, sync width, number of pixels per line)Setup vertical timing parameters for LCD panel (e.g. front porch, back porch, sync width, number of lines per panel)Setup other display parameters (e.g. signal polarity, panel clock frequency, number of clocks per line)Enable conditions that cause interrupt from LCD controller (e.g. vertical compare)Setup base address in external memory of area to DMA display data from.
9 LCD Setup ProcedureSelect clock source (AHB clock, AHB clock divided down, or external oscillator)Load initial display data into external memoryEnable control signals to LCD panel by setting LcdEn bit.System applies contrast voltage VEEApply power to LCD panel by setting LcdPwr bit. This drives CLPOWER active and enables CLD [23:0] to activate display. (see NS9750 Hardware Reference Manual for detailed description of power up and power down sequence)Interrupts will occur during normal operation (e.g. during vertical sync). The application can use these to update the base address used for DMA (e.g. double buffered video display).
10 LCD Panel Clock Generation Source of LCD panel clock is programmable via Clock Configuration Register in SCMAHB clock divided by 1,2,4,8External clock oscillator (LCDCLK) divided by 2LCD controller provides an additional clock divider that can be used to divide the source clock further to generate the LCD panel clock (see NS9750 Hardware Reference Manual for programming limitations on clock divider value)
13 Hints & KinksCan I directly directly connect the NS9750’s LCD interface signals to an LCD display panel?Although there is nothing functionally wrong with this approach, the NS9750’s LCD outputs, with the exception of CLCP(8ma), are rated at only 4ma. Direct connection would only be practical over a few inches of trace. These drive strengths are definitely not applicable to driving a LCD panel via a cable. A single, low-skew, high drive buffer is recommended for applications requiring more drive than the NS9750 can provide. A single device with low-skew is required because the skew between the clock and all of the other signals is the key in meeting the timing requirements of the LCD panel.
14 Hints & KinksMy 24-bit TFT LCD display panel requires differential inputs. How do I interface the NS9750 to it?Most 24-bit TFT panels require LVDS (Low Voltage Differential Signaling) inputs. These typically require an off-the-shelf LVDS serializer device to interface the display controller to the display. The NS9750’s LCD interface can interface directly to the parallel interface of this serializer. Contact the manufacturer of the LCD display for a recommendation on which serializer device to use (e.g. National DS90C385)