1. LANL FEM design proposal S. Butsyk For LANL P-25 group

2. FEM Prototype Addressable 64 FIFO array to store last 64 beam clocks Data being readout by LVL1 trigger request from the FIFO N clocks back in time N is a constant value Fully pipelined design Takes ~4.5 Write clock cycles to store the hit in the FIFO (mainly due to FIFO asynchronous reset synchronization) GOT_HIT Writing into FIFO array Trigger 42 BCO clocks delay Reading from FIFO array GOT_HIT Writing into FIFO array Trigger 42 BCO clocks delay Nothing Data IN …… … CLK FIFO select Reset logic Read Address = Current BCO - N Data OUT 128 word deep FIFO 0 FIFO 1 FIFO 62 FIFO 63 24 bit wide

3. Calibration System Block Diagram FPIX 2.1 DESER INIT PULSER BOARD CALIB CLK 64 FIFO ARRAY 24b x 128 OUTPUT FIFO 24b x 8K ML402 Virtex-4 Board Linux Box 4 24 CLK DATA SHIFT CNTR SHIFT IN CALIB CNTR Par. Port PULSE INWE f = 140 kHz RE DATA OUT f = 40 kHz GOT HIT LVL1 ACCEPT DELAY Full readout prototype chain is tested Uses 2300 (12%) slices and 75 (38%) RAMB16 blocks on VC4VSX35 Xilinx Virtex-4 FPGA Calibration and chip initialization chain controlled by the FPGA “Self-triggered” readout to PC at 140-400 kHz through three Parallel Port

4. Full Readout Calibration Results Realistic triggered readout with 64 FIFO array tested Results of threshold scan repeat FNAL test results   The proposed readout design is working as expected 7 min required for 100 pulses at 64 amplitude settings One pixel tested at a time

5. Next step

6. FEM design proposal Assume FEM receives the data from N chips by fiber at some fixed rate f WRITE_CLK Main design goals  Sort the data by BCO counter  Buffer data for 64 BCO clocks  Store at most 512 hits per BCO  Read the data from certain BCO to output buffer at f READ_CLK speed Try to achieve f WRITE_CLK = f READ_CLK = 300 MHz The following schematics should do the job

7. Writing into “FIFO block” FIFO RST is generated as (LAST|| BCO_CMP)&WRITE_EN LAST (LAST_LONG) flag is generated on WRITE_CLK and BCO_CLK by the first hit in the current BCO LAST signal starts a validity counter Once the counter reaches the threshold, LAST (LAST_LONG) signal is de-asserted Logic checks:  Writng : if LAST=0  Reset the FIFO and start Counter, it is the first hit for this BCO  Reading: if LAST_LONG=0  The hits expired, do not read them out

8. Reading “FIFO block” READ_EN issued on the falling edge of BCO_CLK “FIFO block” readout starts on the rising edge of the BCO_CLK If FIFO not empty on next rising edge  RE_STROBE extends for another BCO_CLK 50 ns latency for data readout compensates possible propagation delays for READ_EN signal READ_EN is a single clock strobe that can be derived from LVL1_ACCEPT

9. DATA flow through the design READ_CLK LogicWRITE_CLK LogicBCO_CLK Logic FIFO DATA_INDATA_IN_4BUFDATA_OU T COUNTER

10. Test results Input data stream at 200 MHz Output from BCO =x”16” 111561 2EE551 000000 222561 000000 333561 000000 444561 000000 555561 2EE561 000000 2EE561 3EF011 2EE561 3E0011 2EE561 0EE021 2EE561 FEE021 2EE561 2EE011 2EE561 2EE560 2EE561 1EE001 FFF561 111561 222561 333561 444561 555561 2EE561 2EE560 2EE561 FFF561 Output from BCO =x”15” 2EE551 Output from BCO =x”02” 0EE021 FEE021 Output from BCO =x”01” 3EF011 3E0011 2EE011 Output from BCO =x”00” 1EE001 READ_CLK frequency 200 MHz