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CWRU EECS 318 EECS 318 CAD Computer Aided Design LECTURE Simulator 1: Synopsys Simulator Instructor: Francis G. Wolff Case Western.

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Presentation on theme: "CWRU EECS 318 EECS 318 CAD Computer Aided Design LECTURE Simulator 1: Synopsys Simulator Instructor: Francis G. Wolff Case Western."— Presentation transcript:

1 CWRU EECS 318 EECS 318 CAD Computer Aided Design LECTURE Simulator 1: Synopsys Simulator Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow

2 CWRU EECS 318 The adder file test bench hierarchy adder_full.vhd adder_full_tb.vhd

3 CWRU EECS 318 adder_full.vhd: full 1-bit adder ARCHITECTURE adder_full_arch OF adder_full IS BEGIN Sum<= ( x XOR y ) XOR Cin; Cout<= ( x AND y ) OR (Cin AND (x OR y)); END; CONFIGURATION adder_full_cfg OF adder_full IS FOR adder_full_arch END FOR; END CONFIGURATION; LIBRARY IEEE; use IEEE.std_logic_1164.all; ENTITY adder_full IS PORT (x, y, Cin: IN std_logic; Sum, Cout: OUT std_logic ); END;

4 CWRU EECS 318 VHDL analyzer: vhdlan For example: > vhdlan -NOEVENT adder_full.vhd Synopsys 1076 VHDL Analyzer Version 2000.06--May 24, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Unix command: vhdlan -NOEVENT Must be done to every vhdl file in the design

5 CWRU EECS 318 VHDL Simulator: vhdlsim Unix command: vhdlsim Starts the text based vhdl simulator For example: > vhdlsim adder_full_cfg Synopsys 1076 VHDL Simulator Version 2000.06-- May 24, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. # Simulator command line prompt #

6 CWRU EECS 318 VHDL Simulator list components: ls vhdlsim list command: ls [-type] [-value] lists the vhdl component types and data values # ls -type ADDER_FULLCOMPONENT INSTANTIATION STATEMENT STANDARDPACKAGE ATTRIBUTESPACKAGE STD_LOGIC_1164PACKAGE _KERNELPROCESS STATEMENT # # ls ADDER_FULL STANDARD ATTRIBUTES STD_LOGIC_1164 _KERNEL After reading in the adder_full.vhd design, a list will show

7 CWRU EECS 318 VHDL Simulator change directory: cd and pwd # ls -type XIN PORT type = STD_LOGIC YIN PORT type = STD_LOGIC CININ PORT type = STD_LOGIC SUMOUT PORT type = STD_LOGIC COUTOUT PORT type = STD_LOGIC _P0PROCESS STATEMENT # cd ADDER_FULL # pwd /ADDER_FULL vhdlsim cd command:cd cd.. pwd cd - change design hierarchy (cd.. go up a level) pwd - display present working directory Alternately, using full paths # ls -type /ADDER_FULL Alternately, using full paths # ls -type /ADDER_FULL

8 CWRU EECS 318 VHDL Simulator assign signal: assign # assign ‘1’ X # ls -value X'U' Y'U' CIN'U' SUM'U' COUT'U' vhdlsim command: assign [-after ] assign a value to a signal # ls -value X'1' Y'U' CIN'U' SUM'U' COUT'U' Alternately, using full paths # assign ‘1’ /ADDER_FULL/X Alternately, using full paths # assign ‘1’ /ADDER_FULL/X

9 CWRU EECS 318 VHDL Simulator run simulation: run # run # assign '1' X # assign '1' Y # assign '0' Cin # ls -value X'1' Y'1' CIN'0' SUM'U' COUT'U' vhdlsim command: run [ ] Use Control-C to cancel a simulation # ls -value X'1' Y'1' CIN'0' SUM ’0' COUT’1' This is what we would expect

10 CWRU EECS 318 VHDL Simulator include vhdlsim command: include [-e] Reads and executes vhdlsim commands from a file -e will displays the lines as it reads them in cd ADDER_FULL assign '1' X assign '1' Y assign '0' Cin ls -value >adder_full.run run ls -value >>adder_full.run exit cd ADDER_FULL assign '1' X assign '1' Y assign '0' Cin ls -value >adder_full.run run ls -value >>adder_full.run exit For example, the file adder_full.vhdlsim contains: > overwrite file >> append to file

11 CWRU EECS 318 VHDL Simulator include using full path names assign '1' /ADDER_FULL/X assign '1' /ADDER_FULL/Y assign '0' /ADDER_FULL/Cin ls -value /ADDER_FULL >adder_full.run run ls -value /ADDER_FULL >>adder_full.run exit assign '1' /ADDER_FULL/X assign '1' /ADDER_FULL/Y assign '0' /ADDER_FULL/Cin ls -value /ADDER_FULL >adder_full.run run ls -value /ADDER_FULL >>adder_full.run exit For example, adder_full.vhdlsim using full path names:

12 CWRU EECS 318 VHDL Simulator trace vhdlsim command: trace Traces vhdl signals on Synopsys Waveform Viewer To best view signals a time element must be added Use View => Full Fit in order to fully view the signals cd ADDER_FULL assign -after 5 '1' X assign -after 5 '1' Y assign -after 5 '0' Cin trace X Y Cin Sum Cout ls -value run ls -value exit cd ADDER_FULL assign -after 5 '1' X assign -after 5 '1' Y assign -after 5 '0' Cin trace X Y Cin Sum Cout ls -value run ls -value exit For example,

13 CWRU EECS 318 VHDL Simulator: abstime, step, next, status vhdlsim command: abstime display the current absolute simulation time so far vhdlsim command: step [ ] step through each vhdl statement, default n=1 vhdlsim command: next [n steps] step through each vhdl statement within current arch vhdlsim command: status show current simulation status

14 CWRU EECS 318 VHDL Simulator: where, environment, restart vhdlsim command: where displays where the process and event stacks vhdlsim command: environment displays the simulator environmental variables vhdlsim command: restart restart the simulation using all previous commands Clean restart: restart /dev/null

15 CWRU EECS 318 VHDL Simulator: help vhdlsim command: help [ ] simulator command help: help ls # help step Subject:STEP Syntax:STEP [n] STEP executes the next "n" lines of VHDL source code. If you omit the argument "n", it executes a single line. STEP enters functions and procedures. STEP does not count or stop on lines that are monitored by an OFF monitor.

16 CWRU EECS 318 VHDL Simulator: unix shell, exit, quit, slist vhdlsim command: ! Execute a unix shell command: !ls vhdlsim command: slist [entity name] display the current source or entity name read in vhdlsim command: quit quit the simulator vhdlsim command: exit exit the simulator

17 CWRU EECS 318 adder_full_tb.vhd: full adder test bench ENTITY adder_full_tb IS PORT (x, y, Cin: IN std_logic; Sum, Cout:OUT std_logic); END; ENTITY adder_full_tb IS PORT (x, y, Cin: IN std_logic; Sum, Cout:OUT std_logic); END; LIBRARY IEEE; use IEEE.std_logic.all;

18 CWRU EECS 318 ARCHITECTURE adder_full_tb_arch OF adder_full_tb IS COMPONENT adder_full PORT (x, y, Cin: IN std_logic; Sum, Cout: OUT std_logic); END COMPONENT; SIGNAL x, y, Cin: std_logic; BEGIN x <= '0', '1' after 50 ns, '0' after 100 ns; y <= '1', '1' after 50 ns, '0' after 100 ns; Cin <= '0', '1' after 50 ns; UUT_ADDER: adder_full PORT MAP(x, y, Cin, Sum, Cout); END; adder_full_tb.vhd: architecture CONFIGURATION adder_full_tb_cfg OF adder_full_tb IS FOR adder_full_tb_arch END FOR; END CONFIGURATION;

19 CWRU EECS 318 VHDL Simulator: test bench # ls ADDER_FULL_TB STANDARD ATTRIBUTES STD_LOGIC_1164 _KERNEL # cd ADDER_FULL_TB # ls SUM _P0 _P2 ADDER_FULL Y COUT _P1 UUT_ADDER X CIN # ls -type SUM OUT PORTtype = STD_LOGIC COUTOUT PORTtype = STD_LOGIC UUT_ADDERCOMPONENT INSTANTIATION ADDER_FULLCOMPONENT X SIGNALtype = STD_LOGIC Unix> vhdlan -NOEVENT adder_full.vhd Unix> vhdlan -NOEVENT adder_full_tb.vhd Unix> vhdlsim adder_full_tb_cfg

20 CWRU EECS 318 VHDL Simulator: run 10 ns # ls -value SUM'U' COUT'U' X'U' Y'U' CIN'U' # run 10 10 NS # ls -value SUM'1' COUT '0' X '0' Y '1' CIN'0' # ls -value SUM'U' COUT'U' X'U' Y'U' CIN'U' # run 10 10 NS # ls -value SUM'1' COUT '0' X '0' Y '1' CIN'0'

21 CWRU EECS 318 VHDL Simulator: run 60 ns # run 60 70 NS # ls -value SUM '1' COUT '1' X'1' Y'1' CIN'1' # quit # run 60 70 NS # ls -value SUM '1' COUT '1' X'1' Y'1' CIN'1' # quit

22 CWRU EECS 318 VHDL Simulator GUI: vhdldbx Unix command: vhdldbx & Starts the VHDL GUI version of vhdlsim Does everything vhdlsim does via menus Use the trace command to view signals First mark the variable with the mouse Then traces -> signals

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