2. 1 ECE1352F – Topic Presentation - ADPLL By Selvakkumaran S

3. 2 Some Analog PLLs have utilized pure digital components before e.g: Charge-pump PLLs utilized Phase Frequency Detector consisting of 3-state finite state machine with two flip-flops D Q CK D Q A B Up Dn ECE1352F – Topic Presentation - ADPLL

4. 3 Digital Phase Detector Digital Loop Filter Digital VCO  in  out All Digital PLLs consist only of digital components The first All Digital PLL was reported by Drogni [1967] ECE1352F – Topic Presentation - ADPLL

5. 4 Why All Digital PLL? *Progress in increasing Performance Speed Reliability *Progress in reducing Size Cost Improvements in digital designs *Portability/ Reusability *Programmability *Testability ECE1352F – Topic Presentation - ADPLL

6. 5 Why All Digital PLL? Solves Problems Related to Analog PLLs(APLL) Sensitivity to DC Drifts Component Saturations Difficulties building higher order loops Initial calibration and periodic adjustments ECE1352F – Topic Presentation - ADPLL

7. 6 Issues of ADPLLs versus APLLs Limitation on operating speed Chip area Power Consumption Worse jitter performance due to D/A converter resolution limitation * Note: The above issues need further exploration[7] as some papers have reported better ADPLL performance. ECE1352F – Topic Presentation - ADPLL

8. 7 Example ADPLL Loop Filter Up/Down control from the Phase Detector Controls the Counter value or the Digital Phase difference – Transfer Function ~ 1/sTi Up/Down Counter ECE1352F – Topic Presentation - ADPLL

9. 8 Example Digital VCO (DCO) Up/Down Counter Value or the Phase Error is utilized to create the clock %N Counter ECE1352F – Topic Presentation - ADPLL

10. 9 ADPLL Design Analysis Z-transform technique [5,6] z domain transfer function Solutions within the unit circle ensures stability ECE1352F – Topic Presentation - ADPLL

11. 10 ADPLL Design Example 1 [2] ECE1352F – Topic Presentation - ADPLL

12. 11 Results [2] Process 0.35  0.25  0.60  0.50  ApproachAD Cell Based Analog (1.9V) Semi- digital AD Cell Based All- Digital Area (mm 2 ) 0.710.090.832.750.71 Power (mW) 100 @500MHz 25105 @400MHz 315 @800MHz 39.6 @100MHz Max.lock Time (cycles) <46<720<16<25<50 Range MHz 45-5108.5-660300-800360-80050-550 Output Jitter 70ps80ps149ps60ps125ps 3.3V Supply

13. 12 Results [2] Shorter Locking in time Better Jitter Performance Better Portability (cell-based design) Reduced circuit complexity Reduced Design Time Note: Some other papers have reported ADPLLs area and power statistics better than APLLs ECE1352F – Topic Presentation - ADPLL

14. 13 ADPLL Design Example 2 [6] A Second order ADPLL H(z)= C 2 (Z-1)+C 1 (Z-1) 2 +C 2 (Z-1)+C 1 H(S)= 2  n S +  n 2 S 2 + 2  n S +  n 2 ECE1352F – Topic Presentation - ADPLL

15. 14 Acquisition Behaviour [6] *ADPLL shows a better performance in terms of the acquisition time ECE1352F – Topic Presentation - ADPLL

16. 15 Phase Jitter Behaviour [6] ECE1352F – Topic Presentation - ADPLL

17. 16 Results [6] Larger lock-in range (~4.5 x APLL) Larger Hold-in Range than APLL Smaller RMS Phase Jitter Digital approach to design Software configurability/ programmability ECE1352F – Topic Presentation - ADPLL

18. 17 No need for off-chip components Technology portability Testability Programmability Fast Acquisition Time Large hold-in range Large lock-in range Better phase jitter performance Simpler design and faster simulation Stability ECE1352F – Topic Presentation - ADPLL

19. 18 Future of ADPLL Digital IP (Intellectual Property) vendors are already creating ADPLL products As technology progress happens skew problems will require ADPLLs within the design components to synchronize the clock signal between various blocks ECE1352F – Topic Presentation - ADPLL

20. 19 1.Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001 2.Ching-Che Chung and Chen-Yi Lee, “An All-Digital Phase- Locked Loop for High Speed Clock Generation, IEEE J. Solid- State Circuits, vol 38, No.2, pp347-351, February 2003 3.Thomas Olsson and Peter Nilsson, “A Digitally Controlled PLL Using a Standard Cell Library”, Lund University, Sweden, www.es.lth.se/home/tonwww.es.lth.se/home/ton 4.Roland E. Best, Phase-Locked Loops, Design, Simulation and Applications, 4th Ed, McGraw-Hill, 1999 (Chapter 4, pp177- 228) 5.Venceslav F, Kroupa, Phase Lock Loops and Frequency Synthesis, Wiley, 2003, (Chapter 10, pp231-254) ECE1352F – Topic Presentation - ADPLL

21. 20 6.Y.R.Shayan, T.Le-Ngoc, “All Digital phase-locked loop: concepts, design and applications”, IEE Procedings, Vol.136, Pt. F. No.1, pp53-56, February 1989 7.Dao-Long Chen, “A Power and Area Efficient CMOS Clock/Data Recovery Circuit for High-Speed Serial Interfaces, IEEE J. of Solid-state Circuits, Vol. 31, No8, pp1170-1176, August 1996 ECE1352F – Topic Presentation - ADPLL

22. 21