1. COMPUTER ORGANIZATIONS CSNB123 NSMS2013 Ver.1Systems and Networking1

2. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O Direct Memory Access (DMA) Interrupt Driven I/O NSMS2013 Ver.1Systems and Networking2

3. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O The processor executes a program that gives it direct control of the I/O operation such as sensing devices status, sending a read/write command and transferring the data NSMS2013 Ver.1Systems and Networking3 I/O Techniques Programmed I/O DMA Interrupt Driven I/O

4. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O (Cont.) I/O Techniques Programmed I/O I/O Command I/O Instruction DMA Interrupt Driven I/O I/O Command  Related to instruction  CPU issues an address, specify the particular I/O module and ED, and an I/O command NSMS2013 Ver.1Systems and Networking4 CommandDescription ControlActivate the ED, give instruction Testtest various status conditions associated - I/O module, ED ReadI/O module to receive an item from the peripheral devices  place it into an internal register WriteI/O module to take a unit of data from the data bus and transmit it to the peripheral

5. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O (Cont.) Example: use programmed I/O to read in a block of data from a peripheral devices into memory Data are read in one word -16 bits, at a time For each word read, CPU must remain in a status checking cycle until it determines that the word is available in the I/O module’s data register Disadvantage; Time consuming – keep CPU busy unnecessarily NSMS2013 Ver.1Systems and Networking5

6. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O (Cont.) I/O Instructions Situation: CPU fetch instruction from memory and the I/O command that the CPU issues to an I/O module to execute the instructions  Instructions are mapped into I/O command Form of instruction depends on the way of ED is addressed – unique identifier or address NSMS2013 Ver.1Systems and Networking6 I/O Techniques Programmed I/O I/O Command I/O Instruction DMA Interrupt Driven I/O

7. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O (Cont.) I/O Instructions I/O module will interpret the address line – determine the command for itself 2 modes of addressing  Memory-mapped I/O  Isolated NSMS2013 Ver.1Systems and Networking7 I/O Techniques Programmed I/O I/O Command I/O Instruction DMA Interrupt Driven I/O

8. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O (Cont.) Memory-mapped I/O A single address space for memory locations and I/O devices The processor treats the status and data registers of I/O modules as memory locations and uses the same machine instructions to access both memory and I/O devices Example: with 10 address lines, a combine 1024 memory locations and I/O addresses can be supported NSMS2013 Ver.1Systems and Networking8

9. COMPUTER ORGANIZATIONS CSNB123 Programmed I/O (Cont.) Isolated I/O Separate address space for both memory and I/O devices Separate memory and I/O select lines needed Small number of I/O instructions Common used NSMS2013 Ver.1Systems and Networking9

10. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts when ready NSMS2013 Ver.1Systems and Networking10 I/O Techniques Programmed I/O Interrupt Driven I/O DMA

11. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) Basic operations 1.CPU issues read command 2.I/O module gets data from peripheral whilst CPU does other work 3.I/O module interrupts CPU 4.CPU requests data 5.I/O module transfers data NSMS2013 Ver.1Systems and Networking11 I/O Techniques Programmed I/O Interrupt Driven I/O DMA I/O Module CPU ED 1 2 3 4 5

12. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) - Input the data from ED to Memory via Processor From I/O View 1.I/O M receives a READ command from CPU 2.The I/O M then leads to read data from an associated ED 3.Once the data are in the module’s data register, the I/O M interrupt the CPU over a control line 4.I/O M then waits until its data are requested by CPU 5.When the request is made, the I/O M places its data on the data bus and then ready for another I/O operation From CPU view 1.CPU issues READ command 2.Then CPU do other works 3.At the end of each instruction cycle, CPU checks for interrupt 4.When there is interrupts from I/O M, then CPU process the interrupt 5.CPU reads the word of data from the I/O M and save it in memory and resumes execution NSMS2013 Ver.1Systems and Networking12

13. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) NSMS2013 Ver.1Systems and Networking13 Technique for Input of a Block of Data

14. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Simple Interrupt Processing StepDescription AED issues an interrupt signal to the CPU B CPU finishes execution of the current instruction before responding to the interrupt C CPU test for the interrupt; if there is one interrupt pending, and then the CPU sends as acknowledgement signal to the ED which issued the interrupt. Get the signal - ED removes its interrupt signals D CPU save info needed to resume the current program at the point of interrupt. Require processor status word (PSW) and address of the next instruction E CPU loads the PC with the entry location of the interrupt handling program - respond to the interrupt NSMS2013 Ver.1Systems and Networking14

15. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Simple Interrupt Processing StepDescription FPC and PSW relating to the interrupted program have been saved on the system stack (place in memory) G The interrupt handles next processes the interrupt. This includes an examination of status information relating to the I/O operation or, other event that caused an interrupt H When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers I The final act is to register the PSW and program counter values from the stack. As a result, the next instruction to be executed will be from the previously interrupted program NSMS2013 Ver.1Systems and Networking15

16. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Two design issues  How does the CPU determine which ED issued the interrupt?  If multiple interrupt occured, how does the CPU decide which one to process? NSMS2013 Ver.1Systems and Networking16

17. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Consider device identification. 4 categories;  Multiple interrupt lines  Software poll  Daisy chain  Bus arbitration NSMS2013 Ver.1Systems and Networking17

18. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Multiple interrupt lines  Straightforward approach  Located between CPU and I/O Modules  Impractical to dedicate more than a few bus lines or CPU pins to interrupt lines Each line attach to multiple I/O modules NSMS2013 Ver.1Systems and Networking18

19. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Software poll  CPU detects interrupt – branches to an interrupt- service routine  job it is to poll each I/O module  determine which module caused the interrupt  Poll – separate command line form  CPU asks each module in turn - slow NSMS2013 Ver.1Systems and Networking19

20. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Software poll  CPU detects interrupt – branches to an interrupt- service routine  job it is to poll each I/O module  determine which module caused the interrupt  Poll – separate command line form  CPU asks each module in turn – slow (time consuming) NSMS2013 Ver.1Systems and Networking20

21. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Daisy chain  Interconnection of computer devices, peripherals, or network nodes in series, one after another  All I/O modules share a common interrupt request line  The interrupt acknowledge line is daisy chained (hardware poll) through the modules  When the CPU senses the interrupt, it send out an interrupt acknowledge  This signal propagates via a series of I/O modules till reach a requesting module  The requesting model respond and place a word on the data lines NSMS2013 Ver.1Systems and Networking21

22. COMPUTER ORGANIZATIONS CSNB123 Interrupt Driven I/O (Cont.) – Design Issue Bus arbitration  I/O Module must claim the bus before it can raise interrupt  Only one module can raise the interrupt at a time  When the CPU detects the interrupt, it responds on the interrupt acknowledge line  The requesting module then places its vector on the data lines NSMS2013 Ver.1Systems and Networking22

23. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) Function Additional Module (hardware) on the system bus Mimic the CPU – control of the system Use system bus for data transferring;  when the processor does not need it  Force CPU to suspend NSMS2013 Ver.1Systems and Networking23 I/O Techniques Programmed I/O Interrupt Driven I/O DMA

24. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) NSMS2013 Ver.1Systems and Networking24 I/O Techniques Programmed I/O Interrupt Driven I/O DMA

25. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) I/O Techniques Programmed I/O Interrupt Driven I/O DMA DMA Block Diagram NSMS2013 Ver.1Systems and Networking25

26. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) I/O Techniques Programmed I/O Interrupt Driven I/O DMA DMA Operation NSMS2013 Ver.1Systems and Networking26 CPU tells DMA controller:-  Read/Write  Device address  Starting address of memory block for data  Amount of data to be transferred CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished

27. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) I/O Techniques Programmed I/O Interrupt Driven I/O DMA DMA Transfer – Cycle stealing NSMS2013 Ver.1Systems and Networking27 DMA controller takes over bus for a cycle Transfer of one word of data Not an interrupt  CPU does not switch context CPU suspended just before it accesses bus Slows down CPU but not as much as CPU doing transfer

28. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) DMA Transfer – Cycle stealing (Cont.) NSMS2013 Ver.1Systems and Networking28 CPU delegates the I/O operation to DMA module The DMA module transfer the entire block of data one at a time directly to or from memory When transfer completes - DMA module sends an interrupt signal to the CPU CPU only involved at the beginning and end of transmission Advantage:  DMA is faster than programmed I/O and Interrupt I/O for multiple-word I/O transfer.

29. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) I/O Techniques Programmed I/O Interrupt Driven I/O DMA DMA Configuration NSMS2013 Ver.1Systems and Networking29 Single-bus, detached DMA Single-bus, integrated DMA I/O I/O bus

30. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) DMA Configuration – Single-bus, detached DMA NSMS2013 Ver.1Systems and Networking30 All modules share the same system bus Each transfer uses bus twice  I/O to DMA then DMA to memory

31. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) DMA Configuration – Single-bus, integrated DMA I/O NSMS2013 Ver.1Systems and Networking31 Controller may support >1 device Each transfer uses bus once  DMA to memory

32. COMPUTER ORGANIZATIONS CSNB123 Direct Memory Access (DMA) (Cont.) DMA Configuration – I/O Bus NSMS2013 Ver.1Systems and Networking32 Separate I/O Bus Bus supports all DMA enabled devices Each transfer uses bus once  DMA to memory