1. Memory System
Unit-IV
4/24/2017
Unit-4 : Memory System

2. Basic concepts (contd..)
Memory
Processor k
-bit
address bus
MAR n
-bit
data bus
Up to 2 k
addressable
MDR
locations
Word length = n
bits
Control lines
( , MFC, etc.) R / W
Recall that the data transfers between a processor and memory involves two
registers MAR and MDR.
If the address bus is k-bits, then the length of MAR is k bits.
If the word length is n-bits, then the length of MDR is n bits.
Control lines include R/W and MFC.
For Read operation R/W = 1 and for Write operation R/W = 0.
4/24/2017
Unit-4 : Memory System

3. Basic concepts (contd..)
Measures for the speed of a memory:
Elapsed time between the initiation of an operation and the completion of an operation is the memory access time.
Minimum time between the initiation of two successive memory operations is memory cycle time.
In general, the faster a memory system, the costlier it is and the smaller it is.
4/24/2017
Unit-4 : Memory System

4. Basic concepts (contd..)
An important design issue is to provide a computer system with as large and fast a memory as possible, within a given cost target.
Several techniques to increase the effective size and speed of the memory:
Cache memory (to increase the effective speed).
Virtual memory (to increase the effective size).
4/24/2017
Unit-4 : Memory System

5. Semiconductor RAM memories
Random Access Memory (RAM) memory unit is a unit where any location can be addressed in a fixed amount of time, independent of the location’s address.
4/24/2017
Unit-4 : Memory System

6. Semiconductor RAM memories
Internal organization of memory chips:
Each memory cell can hold one bit of information.
Memory cells are organized in the form of an array.
One row is one memory word.
All cells of a row are connected to a common line, known as the “word line”.
Word line is connected to the address decoder.
Sense/write circuits are connected to the data input/output lines of the memory chip.
4/24/2017
Unit-4 : Memory System

7. Semiconductor RAM memories
Internal organization of memory chips 7 7 1 1 W • FF FF A W • 1 A 1
Address • • • • • •
Memory
decoder
cells A 2 A 3 W • 15
Sense / Write
Sense / Write
Sense / Write R / W
circuit
circuit
circuit CS
Data input
/output lines: b b b 7 1
4/24/2017
Unit-4 : Memory System

8. Semiconductor RAM memories
Internal organization of memory chips
5-bit row
address W W 1 32 32
5-bit
memory cell
decoder
array W 31
Sense /
Write
circuitry
10-bit
address
32-to-1 R / W
output multiplexer
and CS
input demultiplexer
5-bit column
address
Data
input/output
4/24/2017
Unit-4 : Memory System

9. Semiconductor RAM memories
Static RAMs (SRAMs):
Consist of circuits that are capable of retaining their state as long as the power is applied.
Volatile memories, because their contents are lost when power is interrupted.
Access times of static RAMs are in the range of few nanoseconds.
However, the cost is usually high.
Dynamic RAMs (DRAMs):
Do not retain their state indefinitely.
Contents must be periodically refreshed.
Contents may be refreshed while accessing them for reading.
4/24/2017
Unit-4 : Memory System

10. Static Memories - SRAM
Contain circuits that retains their state as long as power is applied
Implementation
cross connect two inverters to form a latch
transistors act as switches that open or close under the control of the Word Line
4/24/2017
Unit-4 : Memory System

11. Static Memories - SRAM Operation
Write: Sense/ write circuit places value on line b and compliment on b’; forces cell into correct state
Read: Activate Word Line to close switches T1 and T2 ; b carries the value of the circuit; Sense/ write circuit monitors b and b’ and set out accordingly
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Unit-4 : Memory System

12. A Static RAM Cell
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Unit-4 : Memory System

13. CMOS Memory Cell Major advantage of very low power consumption
current flows only when the cell is being accessed
5 volt and 3.3 volt versions
Implementation
transistor pairs forms the inverters
in state 1, point X is high
transistors T3 and T6 are on while T4 and T5 are off
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Unit-4 : Memory System

14. A CMOS Memory Cell
4/24/2017
Unit-4 : Memory System

15. SRAM Operation Transistor arrangement gives stable logic state State 1
C1 high, C2 low
T1 T4 off, T2 T3 on
State 0
C2 high, C1 low
T2 T3 off, T1 T4 on
Address line transistors T5 T6 form switches
Write – apply value to B and complement to B
Read – value is on line B, no rewrite required
feedback
4/24/2017
Unit-4 : Memory System

16. SRAM - Static RAM Bits stored in flip-flop No charges to leak
No refreshing needed when powered - does not need refresh circuits, does not waste time refreshing
More complex cell– more transistors per cell
Larger per bit
More expensive
Faster
Used for cache memory
4/24/2017
Unit-4 : Memory System

17. DRAM - Dynamic RAM Bits stored as charge in capacitors
Charges leak in milliseconds
Need periodic refreshing even when powered – read, rewrite by CPU
Need to refresh → ‘dynamic’ RAM
Simpler construction but need refresh circuits
Smaller per bit
Less expensive
Slower
Used for main memory
4/24/2017
Unit-4 : Memory System

18. DRAM Operation Address line active when bit read or written
Transistor switch high – line closed (current flows)
Write
Voltage to bit line
High for 1, low for 0
Signal (activate) address line
Transfers charge to capacitor
Read
Address line selected
transistor turns on
Charge from capacitor fed via bit line to sense amplifier
Compares with reference value to determine 0 or 1
Capacitor charge must now be restored - rewrite – cycle time!
WRITE
READ
4/24/2017
Unit-4 : Memory System

19. Asynchronous DRAM Internal organization of a Dynamic RAM memory chip
Organized as 4kx4k array.
4096 cells in each row are
divided into 512 groups of 8.
Each row can store 512 bytes.
12 bits to select a row, and 9
bits to select a group in a row.
Total of 21 bits.
Reduce the number of bits by
multiplexing row and column
addresses.
First apply the row address, RAS
signal latches the row address.
Then apply the column address,
CAS signal latches the address.
Timing of the memory unit is
controlled by a specialized unit
which generates RAS and CAS.
This is asynchronous DRAM. R A S
Row
Row
4096 (
512 8 )
address
decoder
cell array
latch CS
Sense / Write A 20 9 - 8
circuits R / W
Column
Column
address
decoder
latch C A S
4/24/2017
Unit-4 : Memory System

20. Semiconductor RAM memories(contd..)
Recall the operation of the memory:
First all the contents of a row are selected based on a row address.
Particular byte is selected based on the column address.
Suppose if we want to access the consecutive bytes in the selected row.
This can be done without having to reselect the row.
Add a latch at the output of the sense circuits in each row.
All the latches are loaded when the row is selected.
Different column addresses can be applied to select and place different bytes on the data lines.
4/24/2017
Unit-4 : Memory System

21. Semiconductor RAM memories(contd..)
Consecutive sequence of column addresses can be applied under the control signal CAS, without reselecting the row.
Allows a block of data to be transferred at a much faster rate than random accesses.
A small collection/group of bytes is usually referred to as a block.
This transfer capability is referred to as the fast page mode feature.
4/24/2017
Unit-4 : Memory System

22. Conventional DRAM Organization
d x w DRAM:
dw total bits organized as d supercells of size w bits
16 x 8 DRAM chip
cols 1 2 3
memory
controller
2 bits /
addr 1
rows 2
supercell
(2,1)
(to CPU) 3
8 bits /
data
4/24/2017
Unit-4 : Memory System
internal row buffer

23. Reading DRAM Supercell (2,1)
Step 1(a): Row access strobe (RAS) selects row 2.
Step 1(b): Row 2 copied from DRAM array to row buffer.
16 x 8 DRAM chip
cols
memory
controller 1 2 3
RAS = 2 2 /
addr 1
rows 2 3 8 /
data
4/24/2017
Unit-4 : Memory System
internal row buffer

24. Reading DRAM Supercell (2,1)
Step 2(a): Column access strobe (CAS) selects column 1.
Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.
16 x 8 DRAM chip
cols
memory
controller 1 2 3
CAS = 1 2 /
addr
supercell
(2,1)
To CPU 1
rows 2 3 8 /
data
supercell
(2,1)
4/24/2017
Unit-4 : Memory System
internal row buffer
internal buffer

25. Basic DRAM read & write Strobe address in two steps 4/24/2017
Unit-4 : Memory System

26. DRAM READ Timing Every DRAM access begins at: Assertion of the RAS_L
2 ways to read: early or late v. CAS
RAS_L
CAS_L
WE_L
OE_L D A
256K x 8
DRAM 9 8
DRAM Read Cycle Time
RAS_L
CAS_L A
Row Address
Col Address
Junk
Row Address
Col Address
Junk
Similar to DRAM write, DRAM read can also be a Early read or a Late read.
In the Early Read Cycle, Output Enable is asserted before CAS is asserted so the data lines will contain valid data one Read access time after the CAS line has gone low.
In the Late Read cycle, Output Enable is asserted after CAS is asserted so the data will not be available on the data lines until one read access time after OE is asserted.
Once again, notice that the RAS line has to remain asserted during the entire time. The DRAM read cycle time is defined as the time between the two RAS pulse.
Notice that the DRAM read cycle time is much longer than the read access time.
Q: RAS & CAS at same time? Yes, both must be low
+2 = 65 min. (Y:45)
WE_L
OE_L D
High Z
Junk
Data Out
High Z
Data Out
Read Access
Time
Output Enable
Delay
4/24/2017
Unit-4 : Memory System
Early Read Cycle: OE_L asserted before CAS_L
Late Read Cycle: OE_L asserted after CAS_L

27. Early Read Sequencing Assert Row Address Assert RAS_L Assert OE_L
Commence read cycle
Meet Row Addr setup time before RAS/hold time after RAS
Assert OE_L
Assert Col Address
Assert CAS_L
Meet Col Addr setup time before CAS/hold time after CAS
Valid Data Out after access time
Disassert OE_L, CAS_L, RAS_L to end cycle
4/24/2017
Unit-4 : Memory System

28. Late Read Sequencing Assert Row Address Assert RAS_L
Commence read cycle
Meet Row Addr setup time before RAS/hold time after RAS
Assert Col Address
Assert CAS_L
Meet Col Addr setup time before CAS/hold time after CAS
Assert OE_L
Valid Data Out after access time
Disassert OE_L, CAS_L, RAS_L to end cycle
4/24/2017
Unit-4 : Memory System