1. RAM (RANDOM ACCESS MEMORY)

2. DEFINITION: THE RAM FAMILY:
A RAM is a volatile chip memory in which both read and write operations can be performed.
A memory unit is a collection of storage cell together with associated circuits needed to transfer information .
It is also called Read-Write Memory(RWM)
THE RAM FAMILY:
It has n-address input lines to access 2^n memory locations and m-data lines to write/read data from/to memory.
The n bit address is placed in Memory Address Register(MAR) to select one of the 2^n memory location
The control signal is used to enable the read and write operations
When read signal is asserted, then the data from memory location gets selected by n-bit address then placed in Memory Buffer Register which is a m-bit register.

3. BLOCK DIAGRAM: ADDRESS n-BITS 1 RAM M ARRAY A . R 2^n-1 READ MBR1
RAM
ARRAY M A R .
2^n-1
READ
MBR
m-DATA LINES
WRITE
D0- Dm-1

4. THE RAM FAMILY:
RAM
BIPOLAR
MOS
STATIC RAM
DYNAMIC RAM
STATIC

5. Semiconductor RAMs may be static or dynamic.
TYPES OF RAM
Semiconductor RAMs may be static or dynamic.
Static RAM uses bipolar or MOS flip flops.
Dynamic RAMs MOSFETS and capacitors which store data.

6. A Static RAM contains an array of flip flop ,one for each stored bit.
Data written in the flip flop remains as long as the dc power is maintained.
The capacity of RAM varies from 64 bits to 1 mega bit.

7. The cells is selected by HIGH value on the ROW and COLUMN lines.
STATIC RAM CELL:
The cells is selected by HIGH value on the ROW and COLUMN lines.
The input data bit(1 or 0) is written into the cell by setting the flip flop for a 1 and resetting the flip flop for a 0 when READ/WRITE line is LOW.
When the READ/WRITE line is HIGH, the flip flop is unaffected.
Then the stored data is gated to the DATA OUT line.

8. LOGIC DIAGRAM
DATA OUT
COLUMN
ROW
& S
& R
DATA IN
READ/WRITE

9. The flip flops in the static memory cell can be constructed using
a)Bipolar junction transistor
b)MOSFETs
BIPOLAR STATIC RAM:
IT consits of two transistors Q1,Q2 that are cross coupled to form a flip flop.
Here the each transistor has three emitters ,viz
1)row select input
2)column select input
3)write input

10. Here there are four transistors Q1,Q2,Q3,Q4.
To select the cell ,both the ROW and COLUMN select must be held HIGH.
When selected , a data bit can be stored in the cell or the content of the cell can be read.
If either ROW or COLUMN select lines is LOW then the memory cell is disabled.
MOS STATIC RAM:
Here there are four transistors Q1,Q2,Q3,Q4.
Out of which Q1 and Q2 acts like switches while Q3 and Q4 acts like active load resistor.
The transistor Q1 conducts and Q2 remains in cut off

11. BASIC STRUCTURE OF A STATIC RAM
RAM has address inputs,data inputs,and a READ/WRITE CONTROL.
When READ/WRITE is HIGH and chip select(cs) is LOW, four data bits from the selected address appears on the data output.
When READ/WRITE is LOW ,the four data bits that are applied to the data inputs are stored at the selected address.

12. LOGIC DIAGRAM FOR A 256*4 STATIC RAM
ADDRESS INPUT
256 X 4
STATIC RAM Y1 Y2 Y3 Y4
DATA OUTPUT
DATA INPUT
R/W EN

13. A 1024 bit device with a 256 x 4 organisation implies that there are 256 rows and 4 columns.Here the memory cell are arranged in an array of 32 x 32 matrix.
OPERATION:
IT has eight input lines(A0 – A7)
Five of the eight address lines (A0 through A4) are decoded by the ROW decoder to select one of the 32 rows.
The remaining 3 address lines (A5 through A7) are used by the COLUMNdecoder to select 4 of 32 columns.
In READ mode , the output buffer are enabled and the four bit from the selected memory location appears on the output(Y1,Y2,Y3,Y4)
In WRITE mode, the input data buffer are enabled and the four bit are routed through input data selector for storage.
During READ and WRITE the CHIP SELECT that is the enable must be LOW.

14. D4 – D1
INPUT BUFFER
ROW DECODER
A0 – A7
32 x 32 memory cell array
R/W
OUTPUT COLUMN DECODER CS
BASIS STRUCTURE OF 256 X 4 STATIC RAM
Y Y Y Y1

15. STATIC RAM IC’S IC 7489-64 BIT STATIC RAM:
IT is arranged as 16 words of 4 bit each.
Data can be written into the memory with the help of data inputs by giving an address to the SELECT input and holding both the enable and write LOW.
Data can be read from any memory location by giving the address to the SELECT input and holding the enable LOW while the write enable HIGH.
ADVANTAGES:
The operation is straight forward and hence easy to understand.

16. PIN DIAGRAM:
VCC SELECT INPUTS DATA SENSE DATA SENSE
INPUT 4 OUTPUT 4 INPUT 3 OUTPUT 3 10 16 15 14 12 11 9 13
B C D D S D3 S3
ME WE D S D S2
SELECT MEMORY DATA SENSE DATA SENSE GND
INPUT A ENABLE INPUT 1 OUTPUT 1 INPUT 2 OUTPUT 2

17. IC – 4K BIT STATIC RAM:
It is a 4096 cell organised as 1024 x 4 bit available in a single pin ic.
The ic uses n-channel silicon gate MOS transistor in a static arrangement.
The CS line allows selection of the expznded memory size.
The WE selects b/w READ and WRITE operations.
The 4 data pins acts as input lines on a WRITE operation, and as output line on a READ operation

18. PIN CONFIGURATION: A6 A5 A4 A3 A0 A1 A2 CS
GND 10 11 12 13 14 15 16 17 18
VCC A7 A8 A9 Y1 Y2 Y3 Y4 WE 1 2 4 5 6 7 8 9 3
IC 2114 RAM

19. TMS 4016 2 KB-STATIC MOS RAM: It is byte organised static RAM.
There are eleven address inputs to select 2048 locations.
The data in (DY1 through DY8) are bidirectional terminals.
These terminals provide both data input during WRITE OPRATION and data output during READ operation.

20. TRUTH TABLE OF TMS 4016: WR CS RD
DY1-DY8
MODE X
DATA INPUT
WRITE 1
DATA OUTPUT
READ
HIGH IMPEDANCE
DEVICE DISABLED
OUTPUT DISABLED

21. DYNAMIC RAM:
The Dynamic Random Access Memory (DRAM) is the lowest cost,high density, RAM available.
It can store binary information in the form of electric charges on the capacitors.
Data that is stored as charge in the capacitors must be recharged as many number of times as possible in order to retain the stored charges.
DRAM makes use of MOS capacitors as memory cell instead of flip flops
ADVANTAGES:
Very large memory array can be constructed at a lower cost.
It offers reduced power consumption and larger storage capacity.
DISADVANTAGES:
MOS capacitor cannot hold the stored charge over an extended period of time.
It has to be refreshed every few seconds.
The circuit becomes complex.

22. The memory cell requires READ and WRITE gatin to operate the cell.
Dynamic MOS RAM cell:
A DRAM consists of arrray of memory cells.in this type of cell ,the transistor acts as a switch
The memory cell requires READ and WRITE gatin to operate the cell.
Column/sense lines
row/control line
Storage capacitor

23. PSEUDO STATIC RAM (PSRAM):
IT is a dynamic RAM with a built in refresh logic.
It can be used even as a static RAM because no external refreshing circuit is required
When it is performing internal refresh it cannot be accessed for read and write operation.

24. ADVANTAGES:
Operating speed is faster
MOS memories are more economical than magnetic core for small systems
Power dissipation is very low
Read out of RAM does not affect the contents stored.