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RAM (RANDOM ACCESS MEMORY). DEFINITION: A RAM is a volatile chip memory in which both read and write operations can be performed. A memory unit is a collection.

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Presentation on theme: "RAM (RANDOM ACCESS MEMORY). DEFINITION: A RAM is a volatile chip memory in which both read and write operations can be performed. A memory unit is a collection."— Presentation transcript:

1 RAM (RANDOM ACCESS MEMORY)

2 DEFINITION: A RAM is a volatile chip memory in which both read and write operations can be performed. A memory unit is a collection of storage cell together with associated circuits needed to transfer information. It is also called Read-Write Memory(R WM) THE RAM FAMILY : It has n-address input lines to access 2^n memory locations and m-data lines to write/read data from/to memory. The n bit address is placed in Memory Address Register(MAR) to select one of the 2^n memory location The control signal is used to enable the read and write operations When read signal is asserted, then the data from memory location gets selected by n-bit address then placed in Memory Buffer Register which is a m-bit register.

3 BLOCK DIAGRAM :. RAM ARRAY MARMAR MBR ADDRESS n- BITS 0 1 2^n-1 m-DATA LINES D0- Dm-1 READ WRITE

4 THE RAM FAMILY: RAM BIPOLAR MOS STATIC STATIC RAM DYNAMIC RAM

5 TYPES OF RAM Semiconductor RAMs may be static or dynamic. Static RAM uses bipolar or MOS flip flops. Dynamic RAMs MOSFETS and capacitors which store data.

6 STATIC RAM A Static RAM contains an array of flip flop,one for each stored bit. Data written in the flip flop remains as long as the dc power is maintained. The capacity of RAM varies from 64 bits to 1 mega bit.

7 STATIC RAM CELL:  The cells is selected by HIGH value on the ROW and COLUMN lines.  The input data bit(1 or 0) is written into the cell by setting the flip flop for a 1 and resetting the flip flop for a 0 when READ/WRITE line is LOW.  When the READ/WRITE line is HIGH, the flip flop is unaffected.  Then the stored data is gated to the DATA OUT line.

8 LOGIC DIAGRAM & & S R COLUMN ROW DATA IN READ/WRITE DATA OUT

9  The flip flops in the static memory cell can be constructed using a)Bipolar junction transistor b)MOSFETs BIPOLAR STATIC RAM: IT consits of two transistors Q1,Q2 that are cross coupled to form a flip flop. Here the each transistor has three emitters,viz 1)row select input 2)column select input 3)write input

10 MOS STATIC RAM: Here there are four transistors Q1,Q2,Q3,Q4. Out of which Q1 and Q2 acts like switches while Q3 and Q4 acts like active load resistor. To select the cell,both the ROW and COLUMN select must be held HIGH. When selected, a data bit can be stored in the cell or the content of the cell can be read. If either ROW or COLUMN select lines is LOW then the memory cell is disabled. The transistor Q1 conducts and Q2 remains in cut off

11 BASIC STRUCTURE OF A STATIC RAM RAM has address inputs,data inputs,and a READ/WRITE CONTROL. When READ/WRITE is HIGH and chip select(cs) is LOW, four data bits from the selected address appears on the data output. When READ/WRITE is LOW,the four data bits that are applied to the data inputs are stored at the selected address.

12 LOGIC DIAGRAM FOR A 256*4 STATIC RAM A0 A1 A2 A3 A4 A5 A6 A7 D1 D2 D3 D4 R/W EN Y1 Y2 Y3 Y4 ADDRE SS INPUT DATA INPUT DATA OUT PUT 256 X 4 STATIC RAM

13 A 1024 bit device with a 256 x 4 organisation implies that there are 256 rows and 4 columns.Here the memory cell are arranged in an array of 32 x 32 matrix. OPERATION: IT has eight input lines(A0 – A7) Five of the eight address lines (A0 through A4) are decoded by the ROW decoder to select one of the 32 rows. The remaining 3 address lines (A5 through A7) are used by the COLUMNdecoder to select 4 of 32 columns. In READ mode, the output buffer are enabled and the four bit from the selected memory location appears on the output(Y1,Y2,Y3,Y4) In WRITE mode, the input data buffer are enabled and the four bit are routed through input data selector for storage. During READ and WRITE the CHIP SELECT that is the enable must be LOW.

14 32 x 32 memory cell array ROW DECODE R R/W CS A0 – A7 INPUT BUFFER OUTPUT COLUMN DECODER D4 – D1 Y4 Y3 Y2 Y1 BASIS STRUCTURE OF 256 X 4 STATIC RAM

15 STATIC RAM IC’S IC BIT STATIC RAM: IT is arranged as 16 words of 4 bit each. Data can be written into the memory with the help of data inputs by giving an address to the SELECT input and holding both the enable and write LOW. Data can be read from any memory location by giving the address to the SELECT input and holding the enable LOW while the write enable HIGH. ADVANTAGES: The operation is straight forward and hence easy to understand.

16 PIN DIAGRAM: B C D D4 S4 D3 S3 ME WE D1 S1 D2 S2 SELECT MEMORY DATA SENSE DATA SENSE GND INPUT A ENABLE INPUT 1 OUTPUT 1 INPUT 2 OUTPUT 2 VCC SELECT INPUTS DATA SENSE DATA SENSE INPUT 4 OUTPUT 4 INPUT 3 OUTPUT 3

17 IC – 4K BIT STATIC RAM: It is a 4096 cell organised as 1024 x 4 bit available in a single pin ic. The ic uses n-channel silicon gate MOS transistor in a static arrangement. The CS line allows selection of the expznded memory size. The WE selects b/w READ and WRITE operations. The 4 data pins acts as input lines on a WRITE operation, and as output line on a READ operation

18 PIN CONFIGURATION: VCC A7 A8 A9 Y1 Y2 Y3 Y4 WE A6 A5 A4 A3 A0 A1 A2 CS GND IC 2114 RAM

19 TMS KB-STATIC MOS RAM: It is byte organised static RAM. There are eleven address inputs to select 2048 locations. The data in (DY1 through DY8) are bidirectional terminals. These terminals provide both data input during WRITE OPRATION and data output during READ operation.

20 TRUTH TABLE OF TMS 4016: WRCSRDDY1-DY8MODE 00XDATA INPUT WRITE 100DATA OUTPUT READ X1XHIGH IMPEDANC E DEVICE DISABLED 101HIGH IMPEDANC E OUTPUT DISABLED

21 DYNAMIC RAM:  The Dynamic Random Access Memory (DRAM) is the lowest cost,high density, RAM available.  It can store binary information in the form of electric charges on the capacitors.  Data that is stored as charge in the capacitors must be recharged as many number of times as possible in order to retain the stored charges.  DRAM makes use of MOS capacitors as memory cell instead of flip flops ADVANTAGES: 1.Very large memory array can be constructed at a lower cost. 2.It offers reduced power consumption and larger storage capacity. DISADVANTAGES: 1.MOS capacitor cannot hold the stored charge over an extended period of time. 2.It has to be refreshed every few seconds. 3.The circuit becomes complex.

22 Dynamic MOS RAM cell: A DRAM consists of arrray of memory cells.in this type of cell,the transistor acts as a switch The memory cell requires READ and WRITE gatin to operate the cell. Storage capacitor row/ contr ol line Column/sen se lines

23 PSEUDO STATIC RAM (PSRAM): IT is a dynamic RAM with a built in refresh logic. It can be used even as a static RAM because no external refreshing circuit is required When it is performing internal refresh it cannot be accessed for read and write operation.

24 ADVANTAGES: 1)Operating speed is faster 2)MOS memories are more economical than magnetic core for small systems 3)Power dissipation is very low 4)Read out of RAM does not affect the contents stored.


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