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Using Cycle Efficiency as a System Designer Metric to Characterize an Embedded DSP and Compare Hard Core vs. Soft Core Advisor Dr. Vishwani D. Agrawal.

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Presentation on theme: "Using Cycle Efficiency as a System Designer Metric to Characterize an Embedded DSP and Compare Hard Core vs. Soft Core Advisor Dr. Vishwani D. Agrawal."— Presentation transcript:

1 Using Cycle Efficiency as a System Designer Metric to Characterize an Embedded DSP and Compare Hard Core vs. Soft Core Advisor Dr. Vishwani D. Agrawal Committee Members Dr. Victor P. Nelson, Dr. Adit D. Singh October 1, 2013 Master’s Project Defense Rathan Raj

2 Outline  Motivation  Background  Problem Statement  Implementation  Results  Conclusion  Limitations and Future Work  References October 1, 20132

3 Motivation  Performance, Power and Area are three conflicting goals, and industry demands that all three aspects be co-optimized.  To obtain a complete performance modeling requires marrying everything from high-level modeling and synthesis to better characterization and verification. October 1, 20133 Performance

4 Background October 1, 20134  What is Characterization?  Characterization over Process, Voltage, Temperature  Performance Metric  Energy Efficiency Metric

5 Background October 1, 20135 Performance Metrics :  Clock Frequency  MIPS  MFLOPS  SPEC ratio  Relative Efficiency  SWAP  Performance per Watt  Cycle Efficiency Source: D. A. Patterson and J. L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, 4 th Edition, Morgan Kaufmann Publishers (Elsevier), 2009 A. Shinde and V. D. Agrawal, “Managing Performance and Efficiency of a Processor,” Proc. 45 th IEEE Southeastern Symp. System Theory, March 2013

6 Background October 1, 20136

7 Background October 1, 2013 7 Source: A. Shinde and V. D. Agrawal, “Managing Performance and Efficiency of a Processor,” Proc. 45 th IEEE Southeastern Symp. System Theory, March 2013 Dr. Agrawal, Lower Power Design of Electronic Circuits, lecture_8.ppt

8 Problem Statement  Can we characterize an embedded DSP in an FPGA and use cycle efficiency to analyze its performance? Also, use cycle efficiency to compare the performance of a Hard Core to a Soft Core. October 1, 20138

9 Implementation  Lattice ECP3 65nm FPGA  Design & Synthesis Tool –Lattice Diamond  Lattice ECP3 DSP unit has cascadable DSP slices that are ideal for power sensitive wireless applications and image signal processing.  Implementation of the function: Multiply Accumulate (MAC) An x Bn + Pn-1 = Pn October 1, 20139 Source : Lattice ECP3 SysDSP usage guide

10 Design Flow October 1, 201310 Design Flow October 1, 201310 Design Entry Synthesis Functional Simulation Fitting Timing Analysis and Simulation Characterization & Programming Design Correct? Timing requirements met? Yes No

11 Power Analysis October 1, 201311 Power Analysis: 65nm Hard DSP at V dd =1.2V, f=280 MHz, No. of execution cycles= 1.5 x10 6 cycles Typical Worst

12 Results October 1, 201312 Power Dissipation and Cycle efficiency Calculations Temperature( 0 C)P Static (mW)P Dyn (mW)P T (mW)E Total (µJ) EPC (nJ/cycle) Cycle Efficiency (η) 10 9 cycles/J 07.41.08.445.3 0.03 33 2510.21.011.260 0.04 25 4514.11.015.182.5 0.054 18 6517.21.018.298 0.065 13 85341.035187 0.125 8 10053.31.054.3292 0.194 5 Worst Process, V dd = 1.2 V, Fmax = 280 MHz, No. of execution cycles = 1.5 x 10 6 cycles.

13 Cycle Efficiency( η) vs. T October 1, 201313 V = 1.2V, Fmax = 280 MHz, No. of Execution cycles = 1.5 x 10 6 cycles.

14 Results October 1, 201314 Performance grade(Process Variation) at different Temperatures and Cycle efficiency Performance grade T=0 0 CFmax Etotal (µJ)EPC (nJ)η (10 9 cycles/J) 6 (worst)281.646.50.03132 7 (typical)305.345.00.03033 8 (best)341.443.50.02936 Performance grade T=25 0 CFmax Etotal (µJ)EPC (nJ) η (10 9 cycles/J) 6 (worst) 281.663.00.04223 7 (typical) 305.358.50.03924 8 (best) 341.457.00.03826 Performance grade T=50 0 CFmax Etotal (µJ) EPC (nJ) η (10 9 cycles/J) 6 (worst) 281.693.00.06216 7 (typical) 305.387.00.05817 8 (best) 341.482.00.05520 Performance grade T= 100 0 CFmax Etotal (µJ) EPC (nJ) η (10 9 cycles/J) 6 (worst)281.6300.00.0205 7 (typical)305.3276.00.1845 8 (best)341.4255.00.1706

15 Performance Grade and η October 1, 201315 Effect of process variation at different Temperatures on Cycle Efficiency V dd = 1.2V, No. of execution cycles = 1.5 x 10 6

16 Comparison of Hard DSP vs. Soft Core (LUT-based)  Device: 90 nm Stratix II GX FPGA  CAD Tool for Design & Synthesis – Quartus 2  MAC operation on both implementations.  Implementation using only the Embedded DSP unit 4 DSP 9x9 multipliers  Implementation using only Logic Elements 337 LUT + 97 Registers October 1, 201316

17 Results Comparison of Hard DSP vs. Soft DSP(LUT) October 1, 2013 17 Resource Utilization F max (MHz)P Static (mW)P Dyn (mW)P I/O (mW)P Total (mW)E Total (µJ) EPC (nJ/cycle) Cycle Efficiency (η) mega cycles/J 4 DSP 9x9 multipliers (Hard Core) 450.05491.0578.8301.81871.6630002.0500 338 LUT + 97 registers (Soft Core) 188.7498.85140.07298.01930.0273504.9204 V dd = 1.2 V, No. of Execution Cycles = 1.5x10 6, and T = 25 0 C

18 Summary  As Temperature increases, cycle efficiency decreases.  From 45 0 C - 100 0 C, there is a 40 % decrease in the cycle efficiency.  The Cycle efficiency calculations at different Performance grades were calculated over the operating temperature range.  Hard DSP vs. Soft DSP (LUT): The dynamic power consumed by the Hard Core was 55 % higher than the dynamic power consumed by the Soft Core. The cycle efficiency of the Hard Core implementation was 150% more than the Soft Core. October 1, 2013 18

19  For system designers who are required to design systems which work robustly under extreme temperature conditions, the cycle efficiency calculations provide valuable insight into the power and performance for the design.  Characterization and Performance analysis over Process, Temperature and Voltage allows the designer to effectively optimize the time and energy requirements of an electronic system. October 1, 2013 19 Conclusion

20 Limitations and Future Work  Characterization was accurate in terms of the design and implementation. However, the Lattice ECP3 device was assumed to be running at a fixed V dd  Tool limitations do not allow frequency and voltage calculations over varying temperature  A Characterization of voltage with varying temperatures and scaling of voltage into the sub-threshold regions will help in better voltage characterization. October 1, 201320

21 Limitations and Future Work  Cycle efficiency can be used in the industry as a performance metric that not only can be applied in the characterization phase but also in the architectural phase for making better engineering judgments during choices of systems and components October 1, 201321

22 References Agrawal, V. D., “Low Power Design of Electronic Circuits,” Power Aware Microprocessors, ELEC-6270, Spring 2013 Altera Corporation, “DSP Blocks in Stratix II and Stratix II GX Devices,” January 2008. Altera Corporation, “Stratix II Architecture,” May 2007. Lattice Semiconductor- Diamond Student Web edition. Lattice Semiconductor, “Lattice ECP3 SysDSP Usage Guide, Technical note TN8112,” February 2012. Lattice Semiconductor, “Lattice Power Consumption and Management for LatticeECP3 Devices Usage Guide, Technical note TN1181,” February 2012. Mirzaei, Shahnam, “Design Methodologies and Architectures for Digital Signal Processing on FPGAs,” in Doctor of Philosophy’s dissertation, University Of California Santa Barbara, June 2010. Patterson, D. A., Hennessy, J. L., Computer Organization & Design: The Hardware/Software Interface, 4 th Edition, Morgan Kaufmann Publishers (Elsevier), 2009 Shinde, A., Agrawal, V. D., “Managing Performance and Efficiency of a Processor,” Proc. 45 th IEEE Southeastern Symp. System Theory, March 2013 October 1, 201322

23 October 1, 201323 Thank You

24 October 1, 201324 Questions?

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