1. Physical Sciences Inc.20 New England Business CenterAndover, MA 01810 VG05-143 Development of the Malleable Signal Processor for the RoadRunner On-board Processing Experiment on the TacSat-2/Joint Warfighting Space Demonstration-1 Spacecraft Robin Coxe, Guillermo Romero, Alireza Pakyari Physical Sciences Inc. Matthew Leary Newgrange Design Inc. Don Fronterhouse Scientific Simulations Inc. James Lyke AFRL Space Vehicles Directorate 2005 MAPLD International Conference Presentation A162 7 September 2005

2. Coxe MAPLD 2005/A162 1 VG05-143 Outline  Joint Warfighter Space Demonstrator (JWS-D) Mission Objectives  TacSat-2/RoadRunner Spacecraft  RoadRunner On-board Processing Experiment (ROPE)  Malleable Signal Processor (MSP) Capabilities  MSP Program Timeline  Lessons Learned

3. Coxe MAPLD 2005/A162 -2 2 VG05-143 TacSat/JWS-D Mission Objectives  Demonstrate rapid fielding of new capability  Responsive Space –6-12 month system development cycles Modular design Standard, Plug-and-Play interfaces “Scaled back reliability and performance” –Stored state to on-orbit in a week –Autonomous on-orbit checkout in a day –2 standard satellite bus options (ISR– 3-axis stabilized/Space Control – small and agile)  Demonstrate responsive support to tactical user –Field tasking and downlink of mission data (imagery, signals) in same pass –Dynamic re-tasking based on internal/external cueing  Collect data to characterize new responsive capabilities –SpaceX Falcon launch vehicle –6-12 month mission life –<3 years in inventory –Keep costs <$20M

4. Coxe MAPLD 2005/A162 -3 3 VG05-143 TacSat-2/RoadRunner Spacecraft Reference: P. Klupar, AFRL/VSSE, “TacSat-2/RoadRunner Overview,” October 2003

5. Coxe MAPLD 2005/A162 -4 4 VG05-143 RoadRunner On-board Processing Experiment (ROPE)  Tri-color/panchromatic imager payload (Nova Sensors, Solvang, CA)  60 Mpixels/sec x 12 bits/pixel x 4 bands = 360 MB/s  Real-time non-uniformity correction, image compression, and RX anomaly detection  Fusion Processor/Solid State Buffer (Space Micro, San Diego, CA) Image Classification Calibrated Imagery ProcessedData Products Lossless Compression and/or Encryption RawImagery Data (ADCCounts) Gain&Offset Corrections Atmospheric Corrections F-2761c NUC NUC NUC NUC Pan Red Green Blue Compression LosslessorLossy Compression LosslessorLossy Compression LosslessorLossy Compression LosslessorLossy RXAnomaly Detection Multiplexer M u l t i p l e x e r CDL Interface Solid State Buffer (8Gbyte) CDLModem FusionProcessor RXTargetRecognition 256Mbits/s G-3668

6. Coxe MAPLD 2005/A162 -5 5 VG05-143 MSP Operational Modes  Personality #1: 16:1 Lossy JPEG  Personality #2: 16:1 Lossy JPEG + RX Anomaly Detection  Personality #3: 4:1 Lossy JPEG  Personality #4: Calibration –No compression core –Buffering in SDRAM in FPGAs #3 and #4 of 256 lines of raw data  Personality #5: ~2:1 Lossless JPEG (compression core developed for future implementation)

7. Coxe MAPLD 2005/A162 -6 6 VG05-143 Malleable Signal Processor (MSP) Flight Engineering Model

8. Coxe MAPLD 2005/A162 -7 7 VG05-143 MSP Diagram & System Specifications  Board dimensions: 9.5” x 8”  Weight (without frame): <1 lb  Power: 5-15 W (typical), 20 W (max.) –Cu strips bonded to the 5 FPGAs with thermal cement and bolted to Al frame  5 VDC, 6A input power System Gates~15,000,000 Logic Cells161,280 BlockRAM (kbits)8640 18x18 multipliers480 Digital Clock Managers60 Distributed RAM (kbits)2240 User I/O Pins2580

9. Coxe MAPLD 2005/A162 -8 8 VG05-143 MSP Feature Summary  5 radiation-tolerant Xilinx XQR2V3000-4BG728N Virtex-II FPGAs  MicroBlaze 32-bit embedded RISC processor in Service FPGA acts as master MSP controller  External SRAM for NUC coefficient storage for the 2 front-end FPGAs  Crosspoint interconnect buses between front & back end FPGAs and Service FPGA  32Mx32 external SDRAM for each of the 4 processing elements  32Mx16 external SDRAM for Service FPGA  100 MHz and 25 MHz clocks  Real-time clock for time synchronization  3.3 V and 1.5 DC power supply  32Mx16 FLASH PROM for configuration bitstream storage  2 GB CompactFLASH card with SystemACE interface to Virtex-II FPGA  Radiation-tolerant configuration PROMs for redundant Service FPGA power-up  Industrial-grade COTS components

10. Coxe MAPLD 2005/A162 -9 9 VG05-143 MSP External Interfaces  Space Micro Inc. Fusion Processor sources commands to MSP via a 230.4 kbps serial port and orchestrates data storage on an 8 GB solid-state buffer via a 125-pin Z-Pack connector  64-bit bi-directional data interface to Fusion Processor  1 pulse per second timing interface  4 x 60.28 MHz image data serial  12-bit parallel inputs  6 x 42.8 MHz ECL serial data downlink interfaces on the Common Data Link (CDL) RF modem  DE-9 RS-232 debug interface

11. Coxe MAPLD 2005/A162 -10 10 VG05-143 MSP System Development Methodology  No TMR or bitstream scrubbing. SEU mitigation strategy is to reconfigure and/or power cycle after SELs –TacSat-2 is a “capabilities-driven” mission: time, manpower, and cost constraints precluded extensive SEU mitigation –Fusion Processor polls MSP with watchdog timer at 100 ms intervals  Extensive use of third-party IP cores –Xilinx CoreGen and MicroBlaze cores –Lossy JPEG core purchased from Amphion Semiconductors (Belfast, Northern Ireland) –Lossless JPEG core developed by Birger Engineering Inc. (Boston, MA) –RX Anomaly Detection core developed at PSI  Used standard VHDL file hierarchy and templates for functional module development, but no formal configuration control –Modules designed for reusability –Employed VHDL package files for parameter definitions

12. Coxe MAPLD 2005/A162 -11 11 VG05-143 MSP Software-adjustable Parameters  The MicroBlaze embedded RISC processor orchestrates the configuration of and flow of data to/from/within the MSP via S/W access to internal control and status registers and On-chip Peripheral Bus (OPB) peripheral driver routines written in C  Software-adjustable parameters include: –Number CDL downlink channels enabled (3 or 6) –Number Imager channels to capture (4 or 1) –Image capture (enabled or disabled) –Transfer data from Solid State Buffer to MSP for CDL downlink –NUC table number (for configuration and uploads) –MSP personality number (for configuration and uploads) –Start time and duration of image capture –RX anomaly detection threshold –Enable direct downlink from MSP to CDL –Enable RX data transfers to Fusion Processor (FP) –Enable 64-bit data transfers from FP to MicroBlaze data bus and store data as FAT16 binary files on the CompactFLASH card For storage of NUC tables, new personalities, data diagnostics, rapid prototyping/debugging

13. Coxe MAPLD 2005/A162 -12 12 VG05-143 MSP Program Timeline  Original vision formulated in an AFRL Space Vehicle Directorate- sponsored Phase I SBIR (presented at MAPLD 2002 – see next slide)  Phase II SBIR contract awarded in May 2003  TacSat-2/ROPE opportunity came about in late August 2003  PSI’s Phase II SBIR program redirected towards MSP development in September 2003  MSP breadboard models fabricated and delivered to PSI in December 2003  Engineering Model #1 MSP hardware delivered to AFRL in Fall 2004  Flight Engineering Model MSP Hardware with frame delivered in Winter 2005  MSP Space Flight Hardware delivered to AFRL on 15 April 2005  PSI continues to provide periodic firmware updates as needed to AFRL pre- and post-launch (scheduled for early 2006)  Flight data assessment (post-launch)

14. Coxe MAPLD 2005/A162 -13 13 VG05-143 Real-Time HSI Processing  Provide end user with customized hyperspectral data products at real-time video rates Noxious CloudofGas F-5679 EVILEVIL

15. Coxe MAPLD 2005/A162 -14 14 VG05-143 Lessons Learned: I  “Responsive Space” is the wave of the future, but the development process is still a work-in-progress –PSI successfully implemented significant additional functionality and new data paths to the MSP after the development effort was well underway –Evolving system specifications, limited financial resources, and a very aggressive development schedule are a volatile combination  Extensive engineering labor and system engineering coordination was required to resolve issues at interfaces between H/W built by different companies –Complicated ICD –Complex interfaces required extensive testing –Geographical separation of team members made I&T resource-intensive  PSI’s decision to fabricate multiple H/W units (10 boards in 2 EM turns) was beneficial to the entire team

16. Coxe MAPLD 2005/A162 -15 15 VG05-143 Lessons Learned: II  MicroBlaze development was subject to “cutting edge” development tools –Upgraded tools 4 times over 2 years – final upgrade to Xilinx EDK and ISE version 6.3 made our lives much happier –New versions were never fully backwards-compatible –Most issues arose at the interface between VHDL functional modules and the MicroBlaze peripheral wrapper VHDL code and C drivers –Required many, many hours of trial and error, but we have become experts!  The use of 3 rd party IP cores is not as straightforward as one might think –Integration of JPEG cores was particularly time-consuming. –We tried 3 approaches: buy IP core outright, oversee development by subcontractor, develop in-house from scratch –No clear winner

17. Coxe MAPLD 2005/A162 -16 16 VG05-143 Concluding Remarks  PSI designed from scratch, prototyped, refined, and delivered MSP flight hardware and firmware in <20 months under an Air Force Phase II SBIR and Phase II Enhancement sponsorship Contract No. F24601-03-C-0086  The MSP platform can be readily re-targeted to other high data volume, on-board DSP and image processing applications without major design modifications –Sonar beamforming and related pipelined FFT processing applications –Hyperspectral image processing –Anomaly and edge detection –Neural computation