1. Picture to be sent (640x480) Displayed Picture (800x600) HOST VGA DE2 Board

2. SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave WBS Wishbone INTERCON Wishbone INTERCON Host (Matlab) VGA Display WBM Message Pack Decoder CheckSum UART RX RX Path WBM Message Pack Encoder CheckSum UART TX TX Path WBM WBS VESA Ctrl VESA Ctrl SG TOP Display Controller Display Controller DC FIFO 100MHz 40MHz SG WBM Memory Management Memory Management SDRAM Arbiter Mem Ctrl WR Mem Ctrl WR Mem Ctrl RD Mem Ctrl RD

3. SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave WBS Wishbone INTERCON Wishbone INTERCON Host (Matlab) VGA Display WBM Message Pack Decoder CheckSum UART RX RX Path WBM Message Pack Encoder CheckSum UART TX TX Path WBM WBS VESA Ctrl VESA Ctrl SG TOP Display Controller Display Controller DC FIFO 100MHz 40MHz SG WBM Memory Management Memory Management SDRAM Arbiter Mem Ctrl WR Mem Ctrl WR Mem Ctrl RD Mem Ctrl RD

4. Flush UART RX MP Dec RAM 1 SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Wr Mem Ctrl Rd SDRAM Arbiter WBS RAM 2 MP Enc UART TX WBM WBS INTERCON Decompressor FIFO VESA Ctrl. VESA Ctrl. req_ln_trig & Pixels, VSync Pixel Manager (Req for Data) Pixel Manager (Req for Data) WBM MUX Synthetic Pic. Gen Synthetic Pic. Gen WBS Flush Dual Clk FIFO WBM wr_rd_bank wr_cnt wr_cnt_en 8 bit Hsync, VSync CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Disp. Reg Frame Reg Frame Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len CRC ERR EOF ERR R1 R2 R1 – Ram 8  16 bits R2 – Ram 16  8 bits - 100 MHz - 40 MHz UART_SE UART_PE OR Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz

6. UART RX MP Dec SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Rd SDRAM Arbiter WBS MP Enc UART TX WBM WBS INTERCON req_ln_trig WBM WBS WBM CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Type Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len Mem Ctrl Wr WBM Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 100 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz SG WBM SG TOP Type Reg Ram initialization / Opcode transmittion:

7. UART RX MP Dec SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Rd SDRAM Arbiter WBS MP Enc UART TX WBM WBS INTERCON req_ln_trig WBM WBS WBM CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Type Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len Mem Ctrl Wr WBM Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 100 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz SG WBM SG TOP SG Reg SDRam initialization:

8. UART RX MP Dec SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Rd SDRAM Arbiter WBS MP Enc UART TX WBM WBS INTERCON req_ln_trig WBM WBS WBM CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Type Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len Mem Ctrl Wr WBM Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 100 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz SG WBM SG TOP SG Reg Detailed Scheme :

9. UART RX MP Dec WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Rd SDRAM Arbiter WBS MP Enc UART TX WBM WBS INTERCON req_ln_trig WBM WBS WBM CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Type Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len Mem Ctrl Wr WBM Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 100 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz SG WBM SG TOP SG Reg Detailed stages 1,2,3 : SDRAM Controller WBS

10. UART RX MP Dec WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Rd SDRAM Arbiter WBS MP Enc UART TX WBM WBS INTERCON req_ln_trig WBM WBS WBM CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Type Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len Mem Ctrl Wr WBM Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 100 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz SG WBM SG TOP SG Reg SDRAM Controller WBS Detailed stage 4 :

11. UART RX MP Dec SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Rd SDRAM Arbiter WBS MP Enc UART TX WBM WBS INTERCON req_ln_trig WBM WBS WBM CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Type Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len Mem Ctrl Wr WBM Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 100 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command Reg Addr TYPE Reg - 133 MHz - 100 MHz System Clock: 100MHz SG WBM SG TOP SG Reg Detailed stages 5,6 :

12. SDRAM Controller WBS Wishbone INTERCON Wishbone INTERCON WBM RX Path WBM TX Path WBM WBS VESA Ctrl VESA Ctrl SG TOP Display Controller Display Controller DC FIFO 100MHz 40MHz SG WBM Memory Management Memory Management TY Ad

13. Frame 2 (640x480) (desired) Frame 1 (800x600) HOST VGA DE2 Board Frame 2 (800x600) (displayed) VGA Sending only changes

14. TX Path Memory Management Memory Management RX Path SDRAM Controller WBS WBM WBS Display Controller Display Controller WBS VGA Display IS42S16400 SDRAM WBM UART VESA Wishbone INTERCON Wishbone INTERCON