1. Chapter No 5 Basic Computer Organization And Design

2. Figure 5-1 Stored Program Organization Address 1101215 Binary Operand Instruction ( Program ) Opcode Memory 4096*16 Operand (Data) Processor Register (Ac) 015 Instruction format

3. Figure 5-2 Direct and Indirect Address Address Opcode I 0 11121415 (a) Instruction Format Operand 457 Memory Add 0 22 AC 1350 300 35 1 Operand1350 Memory 300Add AC Direct addressIndirect address

4. Table 5-1 List Of Register Register symbol BitsRegister nameFunction DR AR AC IR PC TR 16 12 16 12 16 Data Register Address Register Accumulator Instruction Register Program Register Hold Memory Operand Address to Me Processor Register Hold Instruction Code Address of Ins Temporary Data Inpr8 Input Reg Input Character Outr 8Output RegisterHold output Character Temporary Register

5. Figure 5-3 Basic Computer Register and memory. PC 011 Memory 4096 word 16 bits per word IR 0 15 INPR 0 7 AR 011 TR 0 15 OUTR 0 7 DR 0 15 AC 0 15

6. Figure 5-4 Computer Register Connect to Common Bus Memory unit 4096 x 16 AR Bus S2 S1 S0 PC DR AC Adder And logic INPR IR TR OUTR Address 7 1 2 3 4 5 6 E 16-bit common bus

7. Figure 5-5 Basic Computer Instruction Formats (Opcode =000 thr 110 Address OpcodeI 0 11 121415 (a) Memory – Reference Instruction (b) Register Reference Instruction (c) Input- Output Instruction (Opcode=111, I=0) (Opcode =111, I=1) Address 0 1 1 1 0111215 I/O operations 1 1 0 1215

8. Table 5-2 Basic Computer Instruction Hexadecimal Code SymbolI = 0I = 1 Description AND 0xxx8xxxAND memory word to AC ADD1xxx9xxxAdd memory word to AC LDA2xxxAxxxLoad memory word to AC STA3xxxBxxxStore content of AC in memory BUN4xxxCxxxBranch unconditionally BSA5xxxDxxxBranch and save return address ISZ6xxxExxxIncrement and skip if zero CLA7800Clear AC CLE7400Clear E CMA7200Complement AC CME7100Complement E CIR7080Circulate right AC and E CIL7040Circulate left AC and E INC7020Increment AC SPA7010Skip next instruction if AC positive

9. Input-Output Instructions: D 7 IT 3 = p (common to all input-output instructions) IR(n) = B n [ bit in IR(6-11) that specifies the instructions) P:SC  0 INPpB11:AC(0-7)  INPR, FGI  0 1111 1000 0000 0000 F800 OUTpB10:OUTR  AC(0-7), FGO  0 1111 0100 0000 0000 F400 SKIpB9:If (FGI =1) then (PC  PC+1) 1111 0010 0000 0000 F200 SKOpB8:If (FGO =1)then (PC  PC+1) 1111 0001 0000 0000 F100 IONpB7:IEN  1 1111 0000 1000 0000 F080 IOFpB6:IEN  0 1111 0000 0100 0000 F040

10. Memory- Reference Instructions: Symbol:Decoder:RTL:Direct: Indirect: ANDD0AC  AC  M[AR] 00001000 ADDD1AC  AC + M[AR], E  C out 00011001 LDAD2AC  M[AR]00101010 STAD3M[AR]  AC00111011 BUND4PC  AR01001100 BSAD5M[AR]  PC, PC  AR + 101011101 ISZD6M[AR]  M[AR] +1,01101110 If M[AR] + 1 = 0 then PC  PC + 1

11. Register-Reference Instructions: ……Binary Codes……..…………………………..Hex. Oper. B11: 7800 CLA B10: 7400 CLE B9: 7200 CMA B8: 7100 CME B7: 7080 CIR B6: 7040 CIL B5: 7020 INC B4: 7010 SPA B3: 7008 SNA B2: 7004 SZA B1: 7002 SZE B0: 7001 HLT 0 1 1 10 1 0 00 0 0 1 1 10 0 0 0 1 0 0 1 1 10 0 0 10 0 0 1 1 10 0 1 0 0 00 0 0 1 1 10 0 0 1 0 0 0 1 1 11 0 0 00 0 0 1 1 10 0 0 0 1 00 0 0 1 1 10 0 0 0 0 10 0 0 1 1 10 0 1 0 0 0 0 1 1 10 0 0 1 0 0 0 1 1 10 0 0 0 1 00 1 1 10 0 0 0 0 1

12. Table 5-2 Basic Computer Instruction: Hexadecimal Code SymbolI = 0I = 1 Description SNA7008Skip next instruction if AC negative SZA7004Skip next instruction if AC zero SZE7002Skip next instruction if E zero HLT7001Halt computer INPF800Input character to AC OUTF400Output character from AC SKIF200Skip on input flag SKOF100Skip on output flag IONF080Interrupt on IOFF040Interrupt on

13. Instruction Set Completeness: 1)Arithmetic, logical, and shift Instruction. 2)Instruction for moving information to register. 3)Program control Instruction. 4)Input-output Instruction.

14. Figure 5-6 Control Unit Of Basic Computer Instruction Register 11 - 014 13 1215 3 x 8 decoder 7 6 5 4 3 2 1 0 Control logic gates Other inputs I 15 14 ……… 2 1 0 4 x 16 decoder 4-bit Sequence counter (SC) Control outputs Increment (INR) Clear (CLR) Clock

15. Figure 5-7 Control Timing Signal ToTo T1T1 T2T2 T3T3 T4T4 ToTo clock ToTo T1T1 T2T2 T3T3 T4T4 ToTo CLR SC

16. Figure 5-8 Register Transfer Phase S2 S1 S0 Memory Unit AR PC IR ToTo T1T1 Read LD INC LD Address 7 1 2 5 common bus BUS

17. Figure 5-9 Instruction Cycle Flowchart(Initial Config) Start SC  0 AR  PC IR M [AR], PC  PC + 1 Decode operation code in IR (12-14) AR  IR (0-11), I  IR (15) D7D7 I I Execute Register reference Instruction SC  0 Execute Input - output Instruction SC  0 AR  M [AR]Nothing Execute Memory reference Instructions SC  0 (Register or I/O) =1= 0 (Memory reference) I/O =1=0 (register)(indirect) = 1= 0 (direct) T0T0 T1T1 T2T2 T3T3 T3T3 T3T3 T3T3

18. Table 5-3 Execution Of Register Reference Instructions D 7 I’ T 3 = r ( Common All Register Instruction) IR(I)= Bi [0—11 that Specifies The Instruction] r:SC  0Clear SC CLArB 11 :AC  0Clear AC CLErB 10 : E  0Clear E CMArB 9 :AC  ACComplement AC CMErB 8 :E  EComplement E CIRrB 7 :AC  shr AC, AC (15)  E, E  AC(0)Circulate right CIlrB 6 :AC  shl AC, AC (0)  E, E  AC(15)Circulate left INCrB 5 :AC  AC + 1Increment AC SPArB 4 :if(AC(15) = 0) then (PC  PC + 1)Skip if positive SNArB 3 :if(AC(15) = 1) then (PC  PC + 1)Skip if negative SZArB 2 :if (AC = 0) then (PC  PC + 1)Skip if AC is zero SZErB 1 :if (E = 0) then (PC  PC + 1)Skip if E is zero HLTrB 0 :S  0 (S is a start-stop flip flop )Halt Computer

19. Table 5-4 Memory Reference Instruction Operation SymboldecoderSymbolic description ANDD0AC  AC ^ M[AR] ADDD1AC  AC + M[AR], E  C cut LDAD2AC  M[AR] STAD3 M[AR]  AC BUND4PC  AR BSAD5M[AR]  PC, PC  AR +1 ISZD6M[AR]  M[AR] + 1 if M[AR] + 1 = 0 then PC  PC +1

20. Figure 5-10 Example BSA Instruction Execution 0 BSA 135 Next Instruction Subroutine 1 BUN 135 Memory 20 PC= 21 AR= 135 136 (a) Memory, PC, and AR at time T4 0 BSA 135 Next Instruction 21 Subroutine 1 BUN 135 Memory 20 21 135 PC=136 (a) Memory and PC after execution

21. Figure 5-11 Flow Chart for memory Reference Instructions: Memory reference instruction PC  AR SC  0 M [AR]  PC DR M [AR] DR  M [AR]DR  M [MAR]DR M [AR]M[AR]  AC SC  0 AC  AC ^ DR SC  0 AC  AC+DR E  C out SC  0 AC  DR SC  0 AND ADD LDA STA D0T4D0T4 D1T4D1T4 D2T4D2T4 D3T4D3T4 D0T5D0T5 D1T5D1T5 D2T5D2T5 BUNBSAISZ D4T4D4T4 D5T4D5T4 D6T4D6T4 PC  AR SC  0 D5T5D5T5 DR  DR+1 D6T5D6T5 M [AR]  DR If (DR=0) Then (PC  PC + 1) SC  0 D6T6D6T6

22. Figure 5-12 Input-Output Configuration. I/O Terminal Serial communication interface Computer registers and Flip-Flop FGO Printer Receiver Interface OUTR AC INPR Transmitter Interface FGI Keyboard

23. Table 5-5 Input-Output Instruction D7IT3 =p (Common Input – Output Instruction) IR(I) =bi [Bit in IR(6 -11) that specifies instruction) p:SC  0Clear SC INPpB 11 :AC(0-7)  INPRInput character OUTpB 10 :OUTR  AC (0-7), FGO  0Output character SKIpB 9 :If( FGI = 1) then ( PC  PC + 1)Skip on input flag SKOpB 8 :If( FGO = 1) then ( PC  PC + 1)Skip on output flag IONpB 7 :IEN  1Interrupt enable on IOFpB 6 :IEN  0Interrupt enable off

24. Figure 5-13 Flowchart for Interrupt Cycle R =0=1 Instruction Cycle Interrupt Cycle Fetch and decode Instruction Execute Instruction IEN =0 FGI =1 R  1 FGO =0 Store return address In location 0 M[0]  PC Branch to location 1 PC  1 IEN  0 R  0 =0 =1

25. Figure 5-14 Demonstration of the Interrupt Cycle. 0 BUN 1120 Main program I/O Program 1 BUN 0 Memory 0 1 1120 (a) Before interrupt 255 PC=256 256 0 BUN 1120 Main program I/O Program 1 BUN 0 Memory 0 PC=1 1120 (a) After interrupt 255 256

26. Interrupt Cycle: RT0 :AR  0, TR  PC RT1 :M [AR]  TR, PC  0 RT2 :PC  PC + 1, IEN  0, R  0, SC  0 Storing Return Address Condition for R flip-flop T0’ T1’ T2’ (IEN) (FGI + FGO): R  1

27. Figure 5-15 Flowchart for computer Operation Start SC  0, IEN  0, R  0 R AR  PC R’ T 0 IR  M[AR], PC  PC + 1 AR  0,TR  PC R’ T 1 RT 0 M[AR]  TR, PC  0 RT 1 PC  PC+1, IEN  0 R  0, SC  0 RT 2 AR  IR(0—11), I  IR (15) D0 – D7  Decode IR(12-14) D7 =0 I =1 AR  M[AR] Nothing D’ 7 I’ T 3 D’ 7 I T 3 Execute Memory-reference Instruction =1 I Execute Register-reference instruction Execute I/O instruction =0=1 R’ T 2 Interrupt Cycle =1 =0 Instruction Cycle (direct)(Indirect) (Memory-reference)(I/O- reference) D 7 I’ T 3 D 7 I T 3

28. Figure 5-16 Control Gates With AR AR From BusTo Bus LD INRCLR D’ 7 I T3 T2T2 R T0T0 D5D5 T4T4

29. Figure 5-17 Control Single Flip-Flop: pB 7 : IEN  1 pB 6 : IEN  0 RT 2 : IEN  0 IEN J K D7IT3D7IT3 P R T2T2 B6B6 B7 Q

30. Table 5-17 Encoder for Bus Selection circuits. InputsOutputsRegister selected x1x2x3x4x5x6x7S2S1S0for bus 0000000000None 1000000001AR 0100000010PC 0010000011DR 0001000100AC 0000100101IR 0000010110 TR 0000001111 Memory

31. Figure 5-18 Encoder for Bus Selection ENCODER MULTIPLEXER BUS SELECT INPUTS S2 S1 S0 X1 X2 X3 X4 X5 X6 X7

32. Figure 5-19 Circuits associated with AC AC To Bus Adder Logic Circuits Control Gates 16 FROM INPR FROM DR LDINRCLR Cloak 16 8

33. Figure 5-20 Gates controlling the Ld,INR, and CLR OF AC AC To BUS Adder logic LDINRCLR AND ADD DR INPR COM SHR SHL INC CLR r B7B7 B6B6 B5B5 B 11 p D2D2 T5T5 D1D1 D0D0 T5T5 B9B9 16

34. Figure 5-21 One stage of adder and logic circuits J K QAC (i) LD FA ADD CiCi AND C i + 1 DR INPR COM SHR SHL From INPR Bit (i) AC (i + 1) AC (i - 1) DR (i) AC (i)