1. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Digital System Design Course Introduction Lecturer ：吳安宇 Date ： 2005/2/25

2. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 2 台灣大學 吳安宇 教授 Contexts  Digital system design plays an important role in implementing digital functions in modern system-on-chip (SOC) design.  In this course, we will focus on developing the design skills for undergraduate students so that they can be familiar with state-of-the-art digital front-end design skills and design flow.

3. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 3 台灣大學 吳安宇 教授 This course covers:  Firstly, we will introduce the Hardware Description Language (HDL). The chosen HDL is Verilog. We will formally cover  The HDL grammar  The coding guideline  The synthesis guideline  Modern cell-based synthesis flow  Reuse Manual Methodology (RMM), 3rd ed.

4. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 4 台灣大學 吳安宇 教授 This course covers:  Secondly, we will ask students to design an advanced MIPS CPU based on the knowledge of “Computer Organization and Design: The Hardware / Software Interface, 3rd ed” The assignment covers  Instruction set development.  HDL coding and simulation of major blocks such as Arithmetic Logic Unit (ALU) and Control Unit (CU).  Enhanced CPU design with pipelining and control of hazards  Integration of whole design using Verilog and perform simulation.  Evaluate your design using Design Analyzer (Synopsys).  Thirdly, port the MIPS CPU design to FPGA board and perform emulation– use E1-304

5. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 5 台灣大學 吳安宇 教授 Verilog HDL Outlines  Overview of Verilog Hardware Describe Languages  Modeling and Verification with Verilog-HDLs  Logic Design with Behavior Models  Introduction to synthesis with Verilog-HDLs  Synthesis of Combinational Circuits  Synthesis of Sequential Circuits  State machines & Datapath Controllers  Architecture and Algorithm  Coding Style

6. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 6 台灣大學 吳安宇 教授 Advanced MIPS CPU Outlines  Covered in “Computer Architecture” already. Just a brief review:  Overview of MIPS CPU Architecture  Instruction Sets  Arithmetic Logic Unit Design  Control Flow Design  Pipelining Architecture  Forwarding Architecture

7. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 7 台灣大學 吳安宇 教授 Last Year, Their Final Projects…  From single-cycle design to pipelined, hazard-controlled MIPS CPU  Assembler/Compiler for MIPS R2000 instruction set  Demo with running a sorting algorithm

8. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 8 台灣大學 吳安宇 教授 In This Semester, The Final Project…  Design a synthsizable, pipelined, hazard- controlled MIPS machine using Verilog HDL  This machine implements specified basic instruction set of MIPS R2000, and you may add more instructions freely.  Performance/Area will be evaluate as one bonus for your final project.

9. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 9 台灣大學 吳安宇 教授 Course Schedule

10. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 10 台灣大學 吳安宇 教授 電機一館大門

11. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 11 台灣大學 吳安宇 教授 每組設備 (PC, 示波器, 訊號產生器 )

12. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 12 台灣大學 吳安宇 教授 白板及投影機

13. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 13 台灣大學 吳安宇 教授 教室正視圖

14. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 14 台灣大學 吳安宇 教授 教室後視圖

15. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU IP Reuse and Coding guideline

16. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 16 台灣大學 吳安宇 教授 SoC: System on Chip  System A collection of all kinds of components and/or subsystems that are appropriately interconnected to perform the specified functions for end users.  A SoC design is a “product creation process” which  Starts at identifying the end-user needs  Ends at delivering a product with enough functional satisfaction to overcome the payment from the end-user

17. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 17 台灣大學 吳安宇 教授 SoC Definition  Complex IC that integrates the major functional elements of a complete end-product into a single chip or chipset  The SoC design typically incorporates  Programmable processor  On-chip memory  HW accelerating function units (DSP)  Peripheral interfaces (GPIO and AMS blocks)  Embedded software Source: “Surviving the SoC revolution – A Guide to Platform-based Design,” Henry Chang et al, Kluwer Academic Publishers, 1999

18. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 18 台灣大學 吳安宇 教授 SoC Example

19. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 19 台灣大學 吳安宇 教授 SoC Architecture

20. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 20 台灣大學 吳安宇 教授 TI OMAP5910 Dual-Core Processor

21. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 21 台灣大學 吳安宇 教授 SoC 製成演進階段 第一階段 第二階段第三階段 Logic ROM PLL AD/DA Soft I/F Core uP Core DSP Core SRAM Logic ROM SRAM Logic ROM PLL Application Specific Analog Application Specific IP Core AD/DA Soft I/F Core uP Core DSP Core SRAM DRAM Flash Logic Analog Logic Analog DRAM Flash Logic

22. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 22 台灣大學 吳安宇 教授 Engineering Productivity Gap  Engineering productivity has not been keeping up with silicon gate capacity for several years.  Companies have been using larger design teams, making engineers work longer hours, etc., but clearly the limit is being reached.

23. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 23 台灣大學 吳安宇 教授 Why must IP Reuse? Design productivity crisis: Divergence of potential design complexity and designer productivity

24. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 24 台灣大學 吳安宇 教授 Productivity of IP Reusing 2000

25. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 25 台灣大學 吳安宇 教授 Reuse Methodology Manual (RMM)  Promoted by Synopsys and Mentor Graphics  Purpose of the RMM  Allow developers to consistently produce high-quality, reusable macros  Provide integrators with insights into how to select qualified IP  Integrate IP into System-on-Chip (SOC) designs  Broadly accepted by SoC Industry

26. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 26 台灣大學 吳安宇 教授 Outline of the RMM  The overview of the SoC development flow  The process required for developing soft macros  The process of creating hard macros  The process of using IP in an SoC design  Conclude with several sections on more focused topics

27. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 27 台灣大學 吳安宇 教授 Soft IP: Configurable and Portable IP  Soft macro deliverables  Documentation  RTL code, both Verilog and VHDL  Synthesis scripts that work for a variety of technology libraries  Models and testbenches for verifying the macro in the chip environment  Installation scripts

28. Digital System Design Graduate Institute of Electronics Engineering, NTU pp. 28 台灣大學 吳安宇 教授 Creation of the Deliverables -Clocking, registers and avoiding accidental latches -Partitioning -VHDL Specific Guidelines -Verification of compliance Simple, regular structures are easier to get functionally correct, to verify, and to synthesize -Physical design issues -Timing and synthesis issues -Functional design issues -Verification strategies -Manufacturing test -Based on a bottom-up synthesis strategy -A robust set of timing budgets Productization -Simulation -Silicon prototyping Key Idea Design Guidelines Coding Guidelines Synthesis Guidelines Verification Methodology