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Senior Design 1 University of Portland School of Engineering.

Published byAlicia Parrish Modified over 8 years ago

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Presentation on theme: "Senior Design 1 University of Portland School of Engineering."— Presentation transcript:

1 Senior Design 1 University of Portland School of Engineering

2 Project LED Cube Team Stolen Pie –Patrick Bloem –Jess Tate –Devin Pentecost –Caleb Pentecost University of Portland School of Engineering Advisor Dr. Osterberg Industry Representative TBD

3 Senior Design 3 Introduction An Interactive 3D MEMS Display Uses accelerometers “LED Cube” University of Portland School of Engineering

4 Senior Design 4 University of Portland School of Engineering Project Proposal Functional Specification MOSIS Chip Design and Macro Model Creation MOSIS Fabrication (by foundry) Design Document Construct Cube Assemble Circuits Test and Debug Founder's Day Display Software Frameworking Microcontroller Programming Design Approach

5 Senior Design 5 Accomplishments Project Proposal approved Completed Functional Spec v1.0 Completed much of the preliminary design University of Portland School of Engineering

6 Senior Design 6 University of Portland School of Engineering

7 Senior Design 7 Plans Complete component selection, order parts Preliminary designs complete (top-level) –MOSIS –µController University of Portland School of Engineering

8 Senior Design 8 University of Portland School of Engineering Milestones StatusDescription Original Target Previous Target Present Target CompletedProject Proposal9/3/11 CompletedFunctional Specifications ver. 0.99/23/11 PresentSeptember Program Review9/30/11 CompleteFunctional Spec v1.0 approved9/30/11 On TrackComponent Selection Complete10/9/11 On TrackTop Level MOSIS block diagram complete10/16/11 On TrackTop level microcontroller design complete10/23/11 On TrackInitial B2Logic Edif Files Complete10/31/11 On TrackCube mock-up and pinout complete11/6/11 On TrackDesign Document ver 0.911/12/11 On TrackFinal Budget Complete11/12/11 On TrackDesign Document v1.0 approved11/19/11 On TrackFinal MOSIS Edif Files complete11/21/11 On TrackInitial CPLD/FPGA Macro Model Complete12/4/11 On TrackPeer Evaluations/Lab Notebooks Due12/5/11

9 Senior Design 9 Concerns/Issues Concerned about dealing with MOSIS pin limitations. –Solutions are being explored at this time. Macro model is fallback. Industry rep has not been assigned yet. University of Portland School of Engineering

10 Senior Design 10 Conclusions Project is on schedule. Design going well. Animation to showcase the intended functionality. University of Portland School of Engineering

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