1. P. Earle p1 November 16, 2001Electrical SNAP Electrical Design Estimates November 16, 2001 C. Paul Earle Super Nova/Acceleration Probe

2. P. Earle p2 November 16, 2001Electrical Figure 1. Scene Door open / close Focus Control Readout Control Logic FPE Instrument Control Electronics Data Buffering Thermal Control & Monitoring FPA Detectors Shutter Filters CDSA/D DC-DC Converter 1553 I/F Science Data I/F Mass Storage (S/C) ICE SNAP Functional Block Diagram S/C Power S/C C&DH Door Spectrograph Shutter Control Bright Object Detector A/D

3. P. Earle p3 November 16, 2001Electrical 200Sec integration 20Ssec readout 220Sec Science Data Rate FPA Size: 144 CCDs @ 1.6Kx1.6K each ~ 368.6 Mpix 44 HgCdTe @ 2Kx2K each ~ 176 Mpix Spectrograph: 1Kx1K ~ 1Mpix Average Data Rate: ==> 545 Mpix for each 200Sec exposure ==> Data rate (avg) ~ (545Mpix/220Sec) ~ 2.5Mpix/s ~ 40 Mbps @16-bits/pix ~ 20 Mbps (with 2:1 loss-less compression)

4. P. Earle p4 November 16, 2001Electrical CCD Readout ASIC (3” x 3”) each 4 A/Ds 4 CDS chips (Correlated Double Sampling) Bias & Power Generation Sequencer & Clock Drivers 188 Readout ASICs ~ 10 boards (12” x 12”) 18 ASICs each, 9 ASICs per side 2 boxes ~ (13.5”x13.5”x6”) each ~ 9lbs each Total Power: 156Watt (peak), 22 Watt (avg.) Focal Plane Electronics

5. P. Earle p5 November 16, 2001Electrical Requirements: - 70 zones, controlled within +0.5 deg. C of set point - 1 Heater and 1 Temperature Sensor per zone - Each CCD controlled within +0.1 deg. C of set point - Unregulated Heater Power (120Watts) Thermal Control Heater Sensor (AD590) i (T) V+V+ (1 of 258) Current TLM V+V+ V+V+ Figure 2.

6. P. Earle p6 November 16, 2001Electrical CCD Temperatures Mux 16-ch AD506...... A/D Conv. AD 1672 To Memory Power Temp... H/K FIFO + - V-V- V-V- Housekeeping Data Figure 3. CCD temps (188) Mux 16-ch AD506 A/D Conv. AD 1672 To Memory H/K FIFO Zone Temperatures & Other Telemetry points (1 of 11) (1 of 5)

7. P. Earle p7 November 16, 2001Electrical FIFO Buffer Readout Data Buffering To Storage Figure 4. Capture& Control Logic FPGA (1 of 1) Processor Card I/F Digital MUX (4:1) CCD I/F FPE I/F 41 (1 of 188)

8. P. Earle p8 November 16, 2001Electrical On/Off Cmd From PLD Controller Driver Amp I+I+ - + - + Door Actuator Temp Sensor Amp HK Mux + - To Central HK Actuator Current Actuator Voltage Mechanism Control Figure 6. (Door Control Electronics)

9. P. Earle p9 November 16, 2001Electrical CPU UTMC 69R000 Processor & Memory Board Startup ROM EEPROM Memory (Data Processing) Ethernet I/F 1553 I/F xcvr xfmr xcvr xfmr RAM (Data Processing) S/W Dev. Figure 5.

10. P. Earle p10 November 16, 2001Electrical DC/DC Converters +28 VDC Power Distribution Figure 7. - + Current Sense - + Voltage Sense +15 V I+I+ +5 V I+I+ End Items Avg. Power Main Power Board 20 Watts Thermal Control 12 Watts Main Processor 4 Watts Mechanism Control 6 Watts Housekeeping 16 Watts Data Buffering 9 Watts FPE Power Boards 9.4Watts (33Watts peak) FPE Boxes 22Watts (156 Watts peak) Main Box Total: 76.4 Watts Mechanisms 4 Watts Thermal S/S 100 Watts Instrument Total: 202 Watts

11. P. Earle p11 November 16, 2001Electrical Figure 8. Board Estimates Thermal Control (4W) 9 in 10 in Data Buffer (3W) Processor (4W) Mech Control (6W) Housekeeping (16W) Main Power (20W) FPE Power (9.4W)

12. P. Earle p12 November 16, 2001Electrical Figure 9. Main Electronics Box Summary 11 in 19 in 10 in Estimated Mass ~ 44 lbs Estimated Power ~ 76 Watts (avg.) Estimated Size ~ (19 x 11 x 10) in.