1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part I

2. Review We have studied and developed several techniques for simplifying Boolean expressions. These are based on the axioms, definitions and theorems of the Boolean Algebra, applied through the Boolean Calculus. Powerful tabular techniques have been developed for rapid reduction to some minimal cost forms (ie. Karnaugh maps) Now it is time to apply our knowledge and understanding to practical problems, eventually leading us to an understanding of the design issues and approaches in modern computer and network engineering.

3. Goals At the outset of designing a complex system, such as a modern computer or network, it is clear that design is extraordinarily difficult and computationally challenging when performed at the level of fundamental Boolean logic gates. For these reasons modern design approaches are based on hierarchical, component based methods. –Leading to simplified, localized component design, –lowering of design costs, –shifting some aspects of design to the component interface (the compatibility problem). We will now begin to study logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD).

4. Goals We begin our study with simple, but functional circuits –we will construct a small library of useful components –we will seek to identify these components for their re-use potential

5. Goals We begin our study with simple, but functional circuits –we will construct a small library of useful components –we will seek to identify these components for their re-use potential At this stage we will have shifted our understanding from a model based on small-scale integrated circuits (SSI) to a different model based on medium-scale integrated circuits (MSI)

6. Goals We begin our study with simple, but functional circuits –we will construct a small library of useful components –we will seek to identify these components for their re-use potential At this stage we will have shifted our understanding from a model based on small-scale integrated circuits (SSI) to a different model based on medium-scale integrated circuits (MSI) We must consider two distinct types of MSI circuits –Combinational circuits –Sequential circuits We continue now with a study of Combinational circuits.

7. Circuit # 1 : Half-Adder

8. We begin by designing a circuit that will perform numeric (integer) addition of two input values.

9. Circuit # 1 : Half-Adder We begin by designing a circuit that will perform numeric (integer) addition of two input values. Assume that A and B each represent a single data bit, with possible numeric values 0 and 1.

10. Circuit # 1 : Half-Adder We begin by designing a circuit that will perform numeric (integer) addition of two input values. Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. The problem is to design a circuit that is able to model the addition operation: –Assume two inputs, A and B, C A + B S

11. Circuit # 1 : Half-Adder We begin by designing a circuit that will perform numeric (integer) addition of two input values. Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. The problem is to design a circuit that is able to model the addition operation: –Assume two inputs, A and B, –Output: a sum bit, S, C A + B S

12. Circuit # 1 : Half-Adder We begin by designing a circuit that will perform numeric (integer) addition of two input values. Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. The problem is to design a circuit that is able to model the addition operation: –Assume two inputs, A and B, –Output: a sum bit, S, and, a carry bit, C. C A + B S

13. Circuit # 1 : Half-Adder We begin by designing a circuit that will perform numeric (integer) addition of two input values. Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. The problem is to design a circuit that is able to model the addition operation: –Assume two inputs, A and B, –Output: a sum bit, S, and, a carry bit, C. C A + B S HA ABAB S C

14. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 + 0 = 0 (no carry)

15. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 0 + 1 = 1 (no carry)

16. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 + 0 = 1 (no carry)

17. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 + 1 = 0 (with a carry = 1)

18. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 We derive the following expressions for the S and C circuits: Use algebra for simple cases with only a few variables.

19. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 We derive the following expressions for the S and C circuits: S = A’B + AB’

20. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 We derive the following expressions for the S and C circuits: S = A’B + AB’ = A xor B

21. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 We derive the following expressions for the S and C circuits: S = A’B + AB’ = A xor B C = AB

22. Circuit # 1 : Half-Adder We begin the design by constructing a 2-input/2-output truth table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 We derive the following expressions for the S and C circuits: S = A’B + AB’ = A xor B C = AB This circuit is called a Half-Adder.

23. Circuit # 1 : Half-Adder Using the S and C circuit expressions for the Half-Adder circuit: S = A’B + AB’ = A xor B C = AB we can represent the circuit schematically in terms of gate logics. HA ABAB S C

24. Circuit # 1 : Half-Adder Using the S and C circuit expressions for the Half-Adder circuit: S = A’B + AB’ = A xor B C = AB we can represent the circuit schematically in terms of gate logics. HA ABAB S C Half-Adder AND/OR logic HA ABAB S C

25. Circuit # 1 : Half-Adder Using the S and C circuit expressions for the Half-Adder circuit: S = A’B + AB’ = A r B C = AB we can represent the circuit schematically in terms of gate logics. HA ABAB S C Half-Adder AND/OR logic HA ABAB S C HA ABAB S C Half-Adder AND/XOR logic

26. Circuit # 2 : Full-Adder

27. The problem is to design a circuit, called a Full-Adder, that is able to model the addition operation, assuming: –three inputs:A, B and C in, –and two outputs: a sum bit, S, and a carry bit, C out.

28. Circuit # 2 : Full-Adder The problem is to design a circuit, called a Full-Adder, that is able to model the addition operation, assuming: –three inputs:A, B and C in, –and two outputs: a sum bit, S, and a carry bit, C out. Assume that A, B and C in each represent a single data bit, with possible numeric values 0 and 1. The input C in corresponds to a carry bit generated from prior bit additions.

29. Circuit # 2 : Full-Adder The problem is to design a circuit, called a Full-Adder, that is able to model the addition operation, assuming: –three inputs:A, B and C in, –and two outputs: a sum bit, S, and a carry bit, C out. Assume that A, B and C in each represent a single data bit, with possible numeric values 0 and 1. The input C in corresponds to a carry bit generated from prior bit additions. We will eventually generalize the variables –Inputs:A K, B K and C K Outputs:S K and C K+1

30. Circuit # 2 : Full-Adder We begin the design by constructing a 3-input/2-output truth table: C in A B S C out

31. Circuit # 2 : Full-Adder We begin the design by constructing a 3-input/2-output truth table: C in A B S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1

32. Circuit # 2 : Full-Adder We begin the design by constructing a 3-input/2-output truth table: C in A B S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

33. Circuit # 2 : Full-Adder We begin the design by constructing a 3-input/2-output truth table: C in A B S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 This leads to the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’

34. Circuit # 2 : Full-Adder We begin the design by constructing a 3-input/2-output truth table: C in A B S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 This leads to the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = C in AB + C in ’AB + C in A’B + C in AB’

35. Circuit # 2 : Full-Adder We begin the design by constructing a 3-input/2-output truth table: C in A B S C out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 This leads to the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = C in AB + C in ’AB + C in A’B + C in AB’ C in A B S C in FA

36. Circuit # 2 : Full-Adder Proceeding from the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = C out = C in AB + C in ’AB + C in A’B + C in AB’ and recalling that x’y+xy’ = x xor y, we derive the alternative expressions:

37. Circuit # 2 : Full-Adder Proceeding from the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = AB + C in A’B + C in AB’ and recalling that x’y+xy’ = x xor y, we derive the alternative expressions: S = C in ’ (A xor B) + C in (A xor B)’

38. Circuit # 2 : Full-Adder Proceeding from the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = AB + C in A’B + C in AB’ and recalling that x’y+xy’ = x r y, we derive the alternative expressions: S = C in ’ (A xor B) + C in (A xor B)’ = C in xor A xor B

39. Circuit # 2 : Full-Adder Proceeding from the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = AB + C in A’B + C in AB’ and recalling that x’y+xy’ = x r y, we derive the alternative expressions: S = C in ’ (A xor B) + C in (A xor B)’ = C in xor A xor B C out = C in AB + C in ’AB + C in A’B + C in AB’

40. Circuit # 2 : Full-Adder Proceeding from the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = AB + C in A’B + C in AB’ and recalling that x’y+xy’ = x r y, we derive the alternative expressions: S = C in ’ (A xor B) + C in (A xor B)’ = C in xor A xor B C out = C in AB + C in ’AB + C in A’B + C in AB’ = (C in + C in ’)AB + C in (A+A’)B + C in A(B+B’)

41. Circuit # 2 : Full-Adder Proceeding from the expressions: S = C in ’A’B + C in ’AB’ + C in AB + C in A’B’ C out = AB + C in A’B + C in AB’ and recalling that x’y+xy’ = x r y, we derive the alternative expressions: S = C in ’ (A xor B) + C in (A xor B)’ = C in xor A xor B C out = C in AB + C in ’AB + C in A’B + C in AB’ = (C in + C in ’)AB + C in (A+A’)B + C in A(B+B’) = AB + C in B + C in A

42. Circuit # 2 : Full-Adder The representation of the Full-Adder circuit using gate logics is: S = C in xor A xor B C out = AB + C in B + C in A C in A B S C out FA

43. Circuit # 2 : Full-Adder The representation of the Full-Adder circuit using gate logics is: S = C in xor A xor B C out = AB + C in B + C in A C in A B S C out FA Binary Full Adder C in A B S C out FA

44. Circuit # 2 : Full-Adder Adapting the notation to a general set of input and output bits: S K = C K xor A K xor B K C K = A K B K + C K B K + C K A K CKAKBKCKAKBK S K C K+1 FA CKAKBKCKAKBK S K C K+1 FA Binary Full Adder

45. Circuit # 3 : Multi-bit Adder

46. We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B.

47. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } Restrict attention to the 4-bit case (easy to generalize to N-bits).

48. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0

49. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } –Outputs: S = { S 3, S 2, S 1, S 0 } and C out. C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0

50. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } –Outputs: S = { S 3, S 2, S 1, S 0 } and C out. C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0

51. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } –Outputs: S = { S 3, S 2, S 1, S 0 } and C out. HA ABAB S C C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 There is no initial Carry bit.

52. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } –Outputs: S = { S 3, S 2, S 1, S 0 } and C out. C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0

53. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } –Outputs: S = { S 3, S 2, S 1, S 0 } and C out. CKAKBKCKAKBK S K C K+1 FA C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0

54. Circuit # 3 : Multi-bit Adder We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. –Inputs: A = {A 3, A 2, A 1, A 0 } and B = { B 3, B 2, B 1, B 0 } –Outputs: S = { S 3, S 2, S 1, S 0 } and C out. CKAKBKCKAKBK S K C K+1 FA HA ABAB S C C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0

55. Circuit # 3 : Multi-bit Adder Applying our previously determined HA and FA circuits: CKAKBKCKAKBK S K C K+1 FA HA ABAB S C C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 B 3 B 2 B 1 B 0 A 3 A 2 A 1 A 0 S 3 S 2 S 1 S 0 C out 4-bit Binary Adder

56. Circuit # 3 : Multi-bit Adder Applying our previously determined HA and FA circuits: CKAKBKCKAKBK S K C K+1 FA HA ABAB S C C out C 3 C 2 C 1 A 3 A 2 A 1 A 0 +B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 B 3 B 2 B 1 B 0 A 3 A 2 A 1 A 0 S 3 S 2 S 1 S 0 C out HAFA B 3 B 2 B 1 B 0 A 3 A 2 A 1 A 0 S 3 S 2 S 1 S 0 C out 4-bit Binary Adder

57. Summary - Part I We have begun to study logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD). We have studied the design of a number of specific, practical functional circuits, expressed in terms of Boolean expressions and their equivalent logic gates (SSI: Small Scale Integration) with a view to re-using those circuits as components in MSI design. –1-bit Half-Adder –1-bit Full-Adder –Multi-bit Ripple Adder