1. GlueX electronics Collaboration Meeting May, 2004 Paul Smith

2. 12,500 ADC channels 8,200 TDC channels Level 1 Trigger: 200 KHz X 5 KB/event = 1GB/sec Digital Pipeline Deadtimeless ~$3.5M

3. Cockcroft-Walton PMT base

4. Robotic Selective Assembly

5. Electronics Review Andy Lankford (UC Irvine) and Glenn Young (ORNL) at the GlueX Electronics Review - July 23 2003

6. Single channel FADC prototype Test bed for:: SPT converter chip Xilinx chip and software Mentor PCB & FPGA software Intellectual Property (PCI core) Robotic assembly

7. JLab TDC Module

8. “Electronics” View of Trigger/DAQ Digital Pipeline Front End “Digitizer” FE/DAQ Interface Trigger Analog Data To ROC Event Block Buffers Every 64-256 events Every event

9. Photon Rates Level 1 Level 3 Physics Signal Software-based Level 3 System Start @ 10 7  /s Open and unbiased trigger Design for 10 8  /s 15 KHz events to tape Level 1 trigger system With pipeline electronics

10. Selected Review Conclusions: It is important to insure that the requirements on the electronics derive from the physics. The requirements and specifications of the analog front-end electronics are not yet adequately defined. This is coupled to the tentative status of some detector designs. The lack of full definition of detector designs may soon limit progress on electronics design, The manpower resources shown during the review will be inadequate for developing an electronics system of the scope required by GlueX. The decision to standardize all detector readout on a single TDC module design and a single Flash ADC module design is good, and will help simplify the overall electronics system design in a constructive way and conserve valuable engineering resources. The Committee feels that it is desirable to locate these modules in a radiation-free area if possible, in order to improve access.

11. CD-0 5 years to beam! BaBar required 100s of engineer-years GlueX currently has 2 electronics engineers Key detector parameters still undefined Funding profile unknown Management plan unimplemented Welcome new collaborators from Alberta and Oak Ridge!

12. Divide and Conquer F,B Cal FADCs ~3000 channels 8 Bits, 250 MSPS Energy Sum for Level 1 dE/dX FADCs ~3400 channels 125/250 MSPS? 8 Bit log vs 10/12 Bit linear FDC cath FADCs ~6000 channels 62.5 MSPS? Positive input polarity BCal FE Photodetector, discriminator TOF FE HV, discriminator Tracking FE Level 1 TriggerClock/Sync/Calib TDCs ~8200 channels Vertex Tracking Tagger HV, discriminator Active Collimator At least one engineer per sub-system:

13. FADC price/performance space 250 MSPS125 MSPS62.5 MSPS 8 bitsSPT7721 $20AD9289 $11 / 4 channel chip 10 bitsMAX1124 $50 MAX1122 $37 AD9411 $42 ADS5122 $43 / 8 channel chip ADS5277 $40 / 8 channel chip 12 bits AD9226 $20 LTC1741 $13 ADS5221 $14 ADS5273 $65 / 8 channel chip 14 bitsAD5500 $95 LTC1742 $25 ADS5422 $31

14. Next (final?) version of FCAL FADC 6U FADC Clock/ Sync Xilinx V2PRO PICMG 2.16 Small Xilinx Energy sum Ethernet

15. Buy FADCs? Gage LeCroy Acqiris Struck