1. Prototype of the Global Trigger Processor GlueX Collaboration 22 May 2012 Scott Kaneta (skaneta@jlab.org) Fast Electronics Group

2. Presentation Outline Level 1 Trigger Architecture Overview GTP Hardware –Specification –Block Diagram –Prototype GTP Prototype Status Trigger Equations

3. Level 1 Trigger Architecture FCAL (11) BCAL (16) Tagger (2) ST (1)TOF (2) L1 Subsystems (# Crates) Energy Hit Pattern 10Gbps fiber optics Global Trigger Crate: 10Gbps VXS SD Switch A in Global Trigger Crate Trigger Distribution not shown

4. GTP Hardware Specification Altera Stratix IV GX 180 –Pin compatible expansion up to 530k logic elements ($) Support for up to 16 VXS payloads –2x 5-Gbps links per payload 32 LVPECL trigger/clock outputs to TS 4 channel full duplex Fiber transceiver 2 Gb DDR2 Memory –Two independent 1-Gb Interfaces 512 Mb Flash Memory –256 Mb dedication for configuration –256 Mb for code or other 10/100/1000 Ethernet Interface on Front Panel

5. GTP Hardware Block Diagram Configuration Controller CPLD Stratix IV GX 180 Front Panel RJ45 PHY Trigger Out Multi-Image Configuration Flash DDR2 Memory Code Flash Link Up 1 2/2/ SSP Data 1 Link Up 16 2/2/ SSP Data 16...... VXS Backplane Clock, Sync Trig1, Trig2 Nios II Soft Processor(s) Ethernet RGMII 4x Densishield 4/4/ / 32 JTAG High Speed Serial General Purpose Configuration Legend /4/4 Fiber Transceiver

6. GTP Prototype 4 Channel Fiber RJ45 Ethernet Jack 4x 8-Channel LVPECL Trigger/Clock Outputs Altera FPGA Stratix IV GX DDR2 Memory 2x 1-Gb Flash Memory 2x 256-Mb

7. Prototype Evaluation Status TestInitialModerateExtensiveDoneNotes PowerXXXComplete except testing specifications under realistic load ClockingXXLocal oscillators only TransceiversXXPass 5 Gbps from SSP on some slots, need to test all lanes FlashXXR/W config flash from CPLD, Toolkit evaluation of code flash ConfigurationXXNon-volatile configuration from flash DDR2XXEMIF Toolkit Evaluation Trigger OutXXTested with test board, TS testing in upcoming Global Crate test EthernetXXARP and Ping functional using VHDL TCP/IP Stack and MAC FiberEvaluation has not yet begun

8. Ethernet Testing ARP and Ping fully verify hardware –VHDL TCP/IP stack Significant work required for usable interface

9. GTP Equations From Dave Doughty’s presentation January 2008 Z >= TFM*TTOF + EFM*EFCal + RM*((EFCal +1)/(EBCal + 1)) –TTOF - Tracks Forward TOF –EFCal - Energy Forward Calorimeter –EBCal - Energy Barrel Calorimeter Modified from Ben’s implementation for Stratix IV –~2% of FPGA resources Looking for feedback regarding equations –User modification of equations –FPGA density Multiple configurations if necessary

10. GTP Equation

11. Trigger Applications Heavy Photon Search test run –Cluster finding in ECal using CTP –Sliding 3x3 window of crystal energies Calorimeter –221 channels –125 cluster processors

12. Cluster Finding Algorithm + + + + + + ++ Cluster Energy

13. Cluster Finding Design Targeted Xilinx Virtex 5 LX110T Significant timing issues –Design pushes limit of this FPGA Some features not implemented –Control of the number of crystals per cluster –Scalar reporting