1. 1 AVR Session 2 Master : Dr.jafari Authors: M.H Edrisi, hadi.edrisi @@@@ yyyy aaaa hhhh oooo oooo.... cccc oooo mmmm

2. Last Session Summary What Is AVR? What is microcontroller Microcontroller vs Microprocessor Some of the benefits of µC Microcontroller AVR Powered Products 2

3. 3 The History of AVR AVR was developed in the year 1996 by Atmel Corporation The architecture of AVR was developed byAlf-Egil Bogen and Vegard Wollan Alf-Egil Bogen Vegard Wollan RISC microcontroller The AT90S8515 was the first microcontroller which was based on AVR architecture AT90S1200 first microcontroller was AT90S1200 in the year 1997.

4. 4 AVRs are generally classified into six broad groups: tinyAVR — the ATtiny series megaAVR — the ATmega seriesCheap XMEGA — the ATxmega series Application-specific AVR FPSLIC (AVR with FPGA) 32-bit AVRs Basic Families

5. 5 TinyAVR – Less memory, small size, suitable only for simpler application 6–32-pin package 0.5–8 kB program memory Limited peripheral set Basic Families (tinyAVR)

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7. 7 MegaAVR – These are the most popular ones having good amount of memory (upto 256 KB), higher number of inbuilt peripherals and suitable for moderate to complex applications. 4–256 kB program memory 28–100-pin package Extended instruction set (Multiply instructions and instructions for handling larger program memories) Extensive peripheral set Basic Families (megaAVR)

8. 8 XmegaAVR – Used commercially for complex applications, which require large program memory and high speed.4–256 kB program memory 16–384 kB program memory 44–64–100-pin package (A4, A3, A1) Extended performance features, such as DMA, "Event System", and cryptography support. Extensive peripheral set with DACs Basic Families (XMEGA)

9. Other Families Application-specific AVR megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc. FPSLIC (AVR with FPGA) FPGA 5K to 40K gates SRAM for the AVR program code, unlike all other AVRs AVR core can run at up to 50 MHz 32-bit AVRs In 2006 Atmel released microcontrollers based on the new, 32- bit, AVR32 architecture. They include SIMD and DSP instructions, along with other audio and video processing features. This 32-bit family of devices is intended to compete with the ARM based processors. The instruction set is similar to other RISC cores, but is not compatible with the original AVR or any of the various ARM cores. 9

10. 10 Information Series Name Pins Flash Memory Special Feature TinyAVR6-32 0.5-8 KB Small in size MegaAVR28-1004-256KB Extended peripherals XmegaAVR44-10016-384KB DMA, Event System included 8051PICAVR SPEEDSlowModerateFast MEMORYSmallLarge ARCHITECTURECISCRISC ADCNot PresentInbuilt TimersInbuilt PWM ChannelsNot PresentInbuilt

11. 11 ATmega32 ATmega32 ATmel 32KB Flash Programming Memory megaAVR

12. 12Features 1. H igh-performance, Low-power AVR® 8-bit Microcontroller 2.A dvanced RISC Architecture 3. H igh Endurance Non-volatile Memory segments 4. J TAG (IEEE std. 1149.1 Compliant) Interface 5. P eripheral Features 6. S pecial Microcontroller Features 7. I /O and Packages 8. O perating Voltages 9. S peed Grades 10. P ower Consumption at 1 MHz, 3V, 25°C for ATmega32L

13. 13 AVR Architecture Advanced RISC Architectur 131 Powerful Instructions – Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier

14. 14 High Endurance Non-volatile Memory segments Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

15. 15 JTAG (IEEE std. 1149.1 Compliant) Interface 131 Powerful Instructions – Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier

16. 16 Peripheral Features Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and CaptureMode Real Time Counter with Separate Oscillator Four PWM Channels 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

17. 17 Peripheral Features(2) Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On- chip Oscillator On-chip Analog Comparator

18. 18 Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power- save, Power-down, Standby and Extended Standby

19. 19 AVR Architecture I/O and Packages 32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF Operating Voltages 2.7 - 5.5V for ATmega32L – 4.5 - 5.5V for ATmega32

20. 20 AVR Architecture Speed Grades 0 - 8 MHz for ATmega32L 0 - 16 MHz for ATmega32 Power Consumption at 1 MHz, 3V, 25°C for ATmega32L Active: 1.1 mA Idle Mode: 0.35 mA Power-down Mode: < 1 μA

21. End Of Session2 21